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Documents authored by Lesage, Benjamin

Document
Invited Paper
DOI: 10.4230/OASIcs.WCET.2024.3
Invited Paper: Assessing Unchecked Factors for Certification: An Experimental Approach for GPU Cache Parameters

Authors: Cédric Cazanove, Benjamin Lesage, Frédéric Boniol, and Jérôme Ermont

Published in: OASIcs, Volume 121, 22nd International Workshop on Worst-Case Execution Time Analysis (WCET 2024)

Abstract
The certification objectives for airborne electronic hardware defined in AMC20-152A [EASA, 2021] and in AMC20-193 [EASA, 2020] capture some of the activities required for an applicant to embed a hardware platform in a safety-critical avionic system. For COTS (Commercially available Off-The-Shelf) platforms in particular, these objectives require applicants to identify functions, configuration settings, and resources present on the platform, and assess their use by the system. AMC20-152A however recognizes that documentation regarding the behavior of a COTS may be incomplete. There is thus a strong push for applicants to the certification of a COTS to demonstrate their mastery of the platform, to highlight relevant factors (functions, settings, resources, etc.), and their use in their system. We outline in the following a standard approach to the exploration of unchecked factors of a platform, considering existing approaches in the literature, to build such a mastery. Our approach incrementally incorporates and validates knowledge of various factors by including them in micro-simulations compared to experimental ground truth.
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Cédric Cazanove, Benjamin Lesage, Frédéric Boniol, and Jérôme Ermont. Invited Paper: Assessing Unchecked Factors for Certification: An Experimental Approach for GPU Cache Parameters. In 22nd International Workshop on Worst-Case Execution Time Analysis (WCET 2024). Open Access Series in Informatics (OASIcs), Volume 121, pp. 3:1-3:12, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2024)

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@InProceedings{cazanove_et_al:OASIcs.WCET.2024.3,
  author =	{Cazanove, C\'{e}dric and Lesage, Benjamin and Boniol, Fr\'{e}d\'{e}ric and Ermont, J\'{e}r\^{o}me},
  title =	{{Invited Paper: Assessing Unchecked Factors for Certification: An Experimental Approach for GPU Cache Parameters}},
  booktitle =	{22nd International Workshop on Worst-Case Execution Time Analysis (WCET 2024)},
  pages =	{3:1--3:12},
  series =	{Open Access Series in Informatics (OASIcs)},
  ISBN =	{978-3-95977-346-1},
  ISSN =	{2190-6807},
  year =	{2024},
  volume =	{121},
  editor =	{Carle, Thomas},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.WCET.2024.3},
  URN =		{urn:nbn:de:0030-drops-204719},
  doi =		{10.4230/OASIcs.WCET.2024.3},
  annote =	{Keywords: GPU, benchmarks, simulation, certification}
}
Document
DOI: 10.4230/LIPIcs.ECRTS.2019.8
Industrial Application of a Partitioning Scheduler to Support Mixed Criticality Systems

Authors: Stephen Law, Iain Bate, and Benjamin Lesage

Published in: LIPIcs, Volume 133, 31st Euromicro Conference on Real-Time Systems (ECRTS 2019)

Abstract
The ever-growing complexity of safety-critical control systems continues to require evolution in control system design, architecture and implementation. At the same time the cost of developing such systems must be controlled and importantly quality must be maintained. This paper examines the application of Mixed Criticality System (MCS) research to a DAL-A aircraft engine Full Authority Digital Engine Control (FADEC) system which includes studying porting the control system’s software to a preemptive scheduler from a non-preemptive scheduler. The paper deals with three key challenges as part of the technology transitions. Firstly, how to provide an equivalent level of fault isolation to ARINC 653 without the restriction of strict temporal slicing between criticality levels. Secondly extending the current analysis for Adaptive Mixed Criticality (AMC) scheduling to include the overheads of the system. Finally the development of clustering algorithms that automatically group tasks into larger super-tasks to both reduce overheads whilst ensuring the timing requirements, including the important task transaction requirements, are met.
Cite as

Stephen Law, Iain Bate, and Benjamin Lesage. Industrial Application of a Partitioning Scheduler to Support Mixed Criticality Systems. In 31st Euromicro Conference on Real-Time Systems (ECRTS 2019). Leibniz International Proceedings in Informatics (LIPIcs), Volume 133, pp. 8:1-8:22, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2019)

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@InProceedings{law_et_al:LIPIcs.ECRTS.2019.8,
  author =	{Law, Stephen and Bate, Iain and Lesage, Benjamin},
  title =	{{Industrial Application of a Partitioning Scheduler to Support Mixed Criticality Systems}},
  booktitle =	{31st Euromicro Conference on Real-Time Systems (ECRTS 2019)},
  pages =	{8:1--8:22},
  series =	{Leibniz International Proceedings in Informatics (LIPIcs)},
  ISBN =	{978-3-95977-110-8},
  ISSN =	{1868-8969},
  year =	{2019},
  volume =	{133},
  editor =	{Quinton, Sophie},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2019.8},
  URN =		{urn:nbn:de:0030-drops-107455},
  doi =		{10.4230/LIPIcs.ECRTS.2019.8},
  annote =	{Keywords: MCS, DO-178C, Real-Time}
}
Document
DOI: 10.4230/OASIcs.WCET.2009.2283
WCET Analysis of Multi-Level Set-Associative Data Caches

Authors: Benjamin Lesage, Damien Hardy, and Isabelle Puaut

Published in: OASIcs, Volume 10, 9th International Workshop on Worst-Case Execution Time Analysis (WCET'09) (2009)

Abstract
Nowadays, the presence of cache hierarchies tends to be a common trend in processor architectures, even in hardware for real-time embedded systems. Caches are used to fill the gap between the processor and the main memory, reducing access times based on spatial and temporal locality properties of tasks. Cache hierarchies are going even further however at the price of increased complexity. In this paper, we present a safe static data cache analysis method for hierarchies of non-inclusive caches. Using this method, we show that considering the cache hierarchy in the context of data caches allows tighter estimates of the worst case execution time than when considering only the first cache level. We also present considerations about the update policy for data caches.
Cite as

Benjamin Lesage, Damien Hardy, and Isabelle Puaut. WCET Analysis of Multi-Level Set-Associative Data Caches. In 9th International Workshop on Worst-Case Execution Time Analysis (WCET'09). Open Access Series in Informatics (OASIcs), Volume 10, pp. 1-12, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2009)

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@InProceedings{lesage_et_al:OASIcs.WCET.2009.2283,
  author =	{Lesage, Benjamin and Hardy, Damien and Puaut, Isabelle},
  title =	{{WCET Analysis of Multi-Level Set-Associative Data Caches}},
  booktitle =	{9th International Workshop on Worst-Case Execution Time Analysis (WCET'09)},
  pages =	{1--12},
  series =	{Open Access Series in Informatics (OASIcs)},
  ISBN =	{978-3-939897-14-9},
  ISSN =	{2190-6807},
  year =	{2009},
  volume =	{10},
  editor =	{Holsti, Niklas},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.WCET.2009.2283},
  URN =		{urn:nbn:de:0030-drops-22837},
  doi =		{10.4230/OASIcs.WCET.2009.2283},
  annote =	{Keywords: WCET analysis, data cache, multi-level, set-associative}
}
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