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Documents authored by Pinho, Luis Miguel

Document
DOI: 10.4230/OASIcs.AEiC.2026.5
A Rust Framework for Real-Time Parallel Programming

Authors: Hugo Silva, Tiago Carvalho, and Luis Miguel Pinho

Published in: OASIcs, Volume 143, 30th Ada-Europe International Conference on Reliable Software Technologies (AEiC 2026)

Abstract
Real-time systems increasingly rely on parallel execution to meet performance and timing requirements. While several programming languages provide mechanisms for combining real-time and parallel programming, Rust currently lacks dedicated frameworks that address both aspects in an integrated way. In previous work, we proposed a high-level design of a framework for real-time parallel programming in Rust. In this paper, we describe the design of a prototype implementation of this framework as a Rust library. The prototype provides abstractions for creating and managing real-time threads with priorities, as well as thread pools that enable structured parallel execution while respecting priority-based scheduling. We describe the architecture of the prototype, its implementation and illustrate its use through examples. This implementation demonstrates the feasibility of supporting real-time parallel programming patterns in Rust and serves as a foundation for future extensions of the framework.
Cite as

Hugo Silva, Tiago Carvalho, and Luis Miguel Pinho. A Rust Framework for Real-Time Parallel Programming. In 30th Ada-Europe International Conference on Reliable Software Technologies (AEiC 2026). Open Access Series in Informatics (OASIcs), Volume 143, pp. 5:1-5:17, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2026)

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@InProceedings{silva_et_al:OASIcs.AEiC.2026.5,
  author =	{Silva, Hugo and Carvalho, Tiago and Pinho, Luis Miguel},
  title =	{{A Rust Framework for Real-Time Parallel Programming}},
  booktitle =	{30th Ada-Europe International Conference on Reliable Software Technologies (AEiC 2026)},
  pages =	{5:1--5:17},
  series =	{Open Access Series in Informatics (OASIcs)},
  ISBN =	{978-3-95977-425-3},
  ISSN =	{2190-6807},
  year =	{2026},
  volume =	{143},
  editor =	{Filieri, Antonio and Backeman, Peter},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.AEiC.2026.5},
  URN =		{urn:nbn:de:0030-drops-259231},
  doi =		{10.4230/OASIcs.AEiC.2026.5},
  annote =	{Keywords: Real-time systems, Parallel programming, Rust}
}
Document
DOI: 10.4230/OASIcs.AEiC.2026.6
Task-Based Constant Bandwidth Server in the Zephyr Operating System

Authors: Alexander Paschoaletto, Paulo Baltarejo Sousa, Luis Miguel Pinho, and Tiago Carvalho

Published in: OASIcs, Volume 143, 30th Ada-Europe International Conference on Reliable Software Technologies (AEiC 2026)

Abstract
The Constant Bandwidth Server (CBS) is a widely used method to support aperiodic soft real-time tasks in a system that uses dynamic scheduling algorithms, such as Earliest Deadline First (EDF), while providing end-to-end temporal guarantees through bandwidth reservation. We have recently proposed an approach to integrate CBS with the open-source real-time operating system, Zephyr, which involves developing CBS as a separate kernel component that can be shared by multiple execution contexts. In this paper, we propose an alternative approach, which provides each task with a dedicated CBS instance, which enables fine-grained control over task execution. The paper also presents a richer support for EDF scheduling in Zephyr, which is used to support the Task-Based CBS. The proposed method is validated through test cases, demonstrating its efficiency in supporting aperiodic real-time tasks with bandwidth constraints in Zephyr.
Cite as

Alexander Paschoaletto, Paulo Baltarejo Sousa, Luis Miguel Pinho, and Tiago Carvalho. Task-Based Constant Bandwidth Server in the Zephyr Operating System. In 30th Ada-Europe International Conference on Reliable Software Technologies (AEiC 2026). Open Access Series in Informatics (OASIcs), Volume 143, pp. 6:1-6:16, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2026)

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@InProceedings{paschoaletto_et_al:OASIcs.AEiC.2026.6,
  author =	{Paschoaletto, Alexander and Sousa, Paulo Baltarejo and Pinho, Luis Miguel and Carvalho, Tiago},
  title =	{{Task-Based Constant Bandwidth Server in the Zephyr Operating System}},
  booktitle =	{30th Ada-Europe International Conference on Reliable Software Technologies (AEiC 2026)},
  pages =	{6:1--6:16},
  series =	{Open Access Series in Informatics (OASIcs)},
  ISBN =	{978-3-95977-425-3},
  ISSN =	{2190-6807},
  year =	{2026},
  volume =	{143},
  editor =	{Filieri, Antonio and Backeman, Peter},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.AEiC.2026.6},
  URN =		{urn:nbn:de:0030-drops-259246},
  doi =		{10.4230/OASIcs.AEiC.2026.6},
  annote =	{Keywords: Constant Bandwidth Server, Zephyr Operating System}
}
Document
DOI: 10.4230/OASIcs.NG-RES.2026.2
Schedulability Analysis of OpenMP Applications Under Heuristic Task-To-Thread Mapping

Authors: Mohammad Samadi, Tiago Carvalho, Luís Miguel Pinho, and Sara Royuela

Published in: OASIcs, Volume 140, 7th Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2026)

Abstract
Task-to-thread mapping is a key process in parallel applications to achieve the best possible performance. This process is even more challenging when it is required to meet the schedulability and timing requirements of critical systems. In these systems, mapping tasks to threads is usually carried out using static scheduling (i.e., offline mapping) to improve system schedulability, with several approaches being presented in the literature. Nevertheless, there has been little analysis on the impact that these static mapping approaches have on the schedulability of applications exploiting OpenMP, a model increasingly seen as a suitable mechanism to leverage the potential of parallel and heterogeneous processor architectures. This paper, therefore, performs a throughout evaluation of the recently presented heuristic task-to-thread mapping working with different heuristics through allocation and dispatching phases, compared with state-of-the-art, in terms of schedulability. This process is performed using a state-of-the-art schedulability analysis methodology through an integration of our simulator and an existing schedulability toolset. This evaluation allows for identifying the static heuristic mapping approaches that achieve tighter schedulability analysis than other methods in the literature.
Cite as

Mohammad Samadi, Tiago Carvalho, Luís Miguel Pinho, and Sara Royuela. Schedulability Analysis of OpenMP Applications Under Heuristic Task-To-Thread Mapping. In 7th Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2026). Open Access Series in Informatics (OASIcs), Volume 140, pp. 2:1-2:12, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2026)

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@InProceedings{samadi_et_al:OASIcs.NG-RES.2026.2,
  author =	{Samadi, Mohammad and Carvalho, Tiago and Pinho, Lu{\'\i}s Miguel and Royuela, Sara},
  title =	{{Schedulability Analysis of OpenMP Applications Under Heuristic Task-To-Thread Mapping}},
  booktitle =	{7th Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2026)},
  pages =	{2:1--2:12},
  series =	{Open Access Series in Informatics (OASIcs)},
  ISBN =	{978-3-95977-415-4},
  ISSN =	{2190-6807},
  year =	{2026},
  volume =	{140},
  editor =	{Ali, Hazem Ismail and Kurunathan, Harrison},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.NG-RES.2026.2},
  URN =		{urn:nbn:de:0030-drops-254204},
  doi =		{10.4230/OASIcs.NG-RES.2026.2},
  annote =	{Keywords: OpenMP, task-to-thread mapping, heuristics, response time, schedulability}
}
Document
DOI: 10.4230/OASIcs.WCET.2017.10
The P-SOCRATES Timing Analysis Methodology for Parallel Real-Time Applications Deployed on Many-Core Platforms

Authors: Vincent Nelis, Patrick Meumeu Yomsi, and Luís Miguel Pinho

Published in: OASIcs, Volume 57, 17th International Workshop on Worst-Case Execution Time Analysis (WCET 2017)

Abstract
This paper presents the timing analysis methodology developed in the European project P-SOCRATES (Parallel Software Framework for Time-Critical Many-core Systems). This timing analysis methodology is defined for parallel applications that must satisfy both performance and real-time requirements and are executed on modern many-core processor architectures. We discuss the motivation and objectives of the project, the timing analysis flow that we proposed, the tool that has been developed to automatize it, and finally we report on some of the preliminary results that we have obtained when applying this methodology to the three application use-cases of the project.
Cite as

Vincent Nelis, Patrick Meumeu Yomsi, and Luís Miguel Pinho. The P-SOCRATES Timing Analysis Methodology for Parallel Real-Time Applications Deployed on Many-Core Platforms. In 17th International Workshop on Worst-Case Execution Time Analysis (WCET 2017). Open Access Series in Informatics (OASIcs), Volume 57, pp. 10:1-10:9, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2017)

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@InProceedings{nelis_et_al:OASIcs.WCET.2017.10,
  author =	{Nelis, Vincent and Yomsi, Patrick Meumeu and Pinho, Lu{\'\i}s Miguel},
  title =	{{The P-SOCRATES Timing Analysis Methodology for Parallel Real-Time Applications Deployed on Many-Core Platforms}},
  booktitle =	{17th International Workshop on Worst-Case Execution Time Analysis (WCET 2017)},
  pages =	{10:1--10:9},
  series =	{Open Access Series in Informatics (OASIcs)},
  ISBN =	{978-3-95977-057-6},
  ISSN =	{2190-6807},
  year =	{2017},
  volume =	{57},
  editor =	{Reineke, Jan},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.WCET.2017.10},
  URN =		{urn:nbn:de:0030-drops-73120},
  doi =		{10.4230/OASIcs.WCET.2017.10},
  annote =	{Keywords: Timing analysis, many-core platform}
}
Document
DOI: 10.4230/OASIcs.WCET.2016.6
The Variability of Application Execution Times on a Multi-Core Platform

Authors: Vincent Nélis, Patrick Meumeu Yomsi, and Luís Miguel Pinho

Published in: OASIcs, Volume 55, 16th International Workshop on Worst-Case Execution Time Analysis (WCET 2016)

Abstract
It is a known fact that processes running concurrently on different cores in a multicore environment interfere with each other on the processor shared resources. The contention on these shared resources considerably slows down the execution on every core since sometimes the cores must stall while their requests to access the resources are being served. But by how much the execution may be slowed down due to this interference? In this paper we answer this question with numbers coming from experimentation. That is, we quantify the magnitude of the impact of the interference on the execution time by running programs taken from the TACLeBench benchmark suite, a popular benchmark suite in the real-time research community, on the first generation of Kalray manycore processor family, the MPPA-256 (the development board) that goes by the codename "Andey".
Cite as

Vincent Nélis, Patrick Meumeu Yomsi, and Luís Miguel Pinho. The Variability of Application Execution Times on a Multi-Core Platform. In 16th International Workshop on Worst-Case Execution Time Analysis (WCET 2016). Open Access Series in Informatics (OASIcs), Volume 55, pp. 6:1-6:11, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2016)

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@InProceedings{nelis_et_al:OASIcs.WCET.2016.6,
  author =	{N\'{e}lis, Vincent and Yomsi, Patrick Meumeu and Pinho, Lu{\'\i}s Miguel},
  title =	{{The Variability of Application Execution Times on a Multi-Core Platform}},
  booktitle =	{16th International Workshop on Worst-Case Execution Time Analysis (WCET 2016)},
  pages =	{6:1--6:11},
  series =	{Open Access Series in Informatics (OASIcs)},
  ISBN =	{978-3-95977-025-5},
  ISSN =	{2190-6807},
  year =	{2016},
  volume =	{55},
  editor =	{Schoeberl, Martin},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.WCET.2016.6},
  URN =		{urn:nbn:de:0030-drops-68994},
  doi =		{10.4230/OASIcs.WCET.2016.6},
  annote =	{Keywords: Execution time variability, timing analysis, WCET estimates, multi-cores, many-cores}
}
Document
DOI: 10.4230/OASIcs.WCET.2014.63
The Challenge of Time-Predictability in Modern Many-Core Architectures

Authors: Vincent Nélis, Patrick Meumeu Yomsi, Luís Miguel Pinho, José Carlos Fonseca, Marko Bertogna, Eduardo Quiñones, Roberto Vargas, and Andrea Marongiu

Published in: OASIcs, Volume 39, 14th International Workshop on Worst-Case Execution Time Analysis (2014)

Abstract
The recent technological advancements and market trends are causing an interesting phenomenon towards the convergence of High-Performance Computing (HPC) and Embedded Computing (EC) domains. Many recent HPC applications require huge amounts of information to be processed within a bounded amount of time while EC systems are increasingly concerned with providing higher performance in real-time. The convergence of these two domains towards systems requiring both high performance and a predictable time-behavior challenges the capabilities of current hardware architectures. Fortunately, the advent of next-generation many-core embedded platforms has the chance of intercepting this converging need for predictability and high-performance, allowing HPC and EC applications to be executed on efficient and powerful heterogeneous architectures integrating general-purpose processors with many-core computing fabrics. However, addressing this mixed set of requirements is not without its own challenges and it is now of paramount importance to develop new techniques to exploit the massively parallel computation capabilities of many-core platforms in a predictable way.
Cite as

Vincent Nélis, Patrick Meumeu Yomsi, Luís Miguel Pinho, José Carlos Fonseca, Marko Bertogna, Eduardo Quiñones, Roberto Vargas, and Andrea Marongiu. The Challenge of Time-Predictability in Modern Many-Core Architectures. In 14th International Workshop on Worst-Case Execution Time Analysis. Open Access Series in Informatics (OASIcs), Volume 39, pp. 63-72, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2014)

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@InProceedings{nelis_et_al:OASIcs.WCET.2014.63,
  author =	{N\'{e}lis, Vincent and Yomsi, Patrick Meumeu and Pinho, Lu{\'\i}s Miguel and Fonseca, Jos\'{e} Carlos and Bertogna, Marko and Qui\~{n}ones, Eduardo and Vargas, Roberto and Marongiu, Andrea},
  title =	{{The Challenge of Time-Predictability in Modern Many-Core Architectures}},
  booktitle =	{14th International Workshop on Worst-Case Execution Time Analysis},
  pages =	{63--72},
  series =	{Open Access Series in Informatics (OASIcs)},
  ISBN =	{978-3-939897-69-9},
  ISSN =	{2190-6807},
  year =	{2014},
  volume =	{39},
  editor =	{Falk, Heiko},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.WCET.2014.63},
  URN =		{urn:nbn:de:0030-drops-46050},
  doi =		{10.4230/OASIcs.WCET.2014.63},
  annote =	{Keywords: Time-Predictability, Many-Cores, Multi-Cores, Timing Analysis}
}
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