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Documents authored by Ravi, S. S.

Found 2 Possible Name Variants:

Ravi, S. S.

Document
DOI: 10.4230/LIPIcs.ECRTS.2017.12
The Multi-Domain Frame Packing Problem for CAN-FD

Authors: Prachi Joshi, Haibo Zeng, Unmesh D. Bordoloi, Soheil Samii, S. S. Ravi, and Sandeep K. Shukla

Published in: LIPIcs, Volume 76, 29th Euromicro Conference on Real-Time Systems (ECRTS 2017)

Abstract
The Controller Area Network with Flexible Data-Rate (CAN-FD) is a new communication protocol to meet the bandwidth requirements for the constantly growing volume of data exchanged in modern vehicles. The problem of frame packing for CAN-FD, as studied in the literature, assumes a single sub-system where one CAN-FD bus serves as the communication medium among several Electronic Control Units (ECUs). Modern automotive electronic systems, on the other hand, consist of several sub-systems, each facilitating a certain functional domain such as powertrain, chassis and suspension. A substantial fraction of all signals is exchanged across sub-systems. In this work, we study the frame packing problem for CAN-FD with multiple sub-systems, and propose a two-stage optimization framework. In the first stage, we pack the signals into frames with the objective of minimizing the bandwidth utilization. In the second stage, we extend Audsley's algorithm to assign priorities/identifiers to the frames. In case the resulting solution is not schedulable, our framework provides a potential repacking method. We propose two solution approaches: (a) an Integer Linear Programming (ILP) formulation that provides an optimal solution but is computationally expensive for industrial-size problems; and (b) a greedy heuristic that scales well and provides solutions that are comparable to optimal solutions. Experimental results show the efficiency of our optimization framework in achieving feasible solutions with low bandwidth utilization. The results also show a significant improvement over the case when there is no cross-domain consideration (as in prior work).
Cite as

Prachi Joshi, Haibo Zeng, Unmesh D. Bordoloi, Soheil Samii, S. S. Ravi, and Sandeep K. Shukla. The Multi-Domain Frame Packing Problem for CAN-FD. In 29th Euromicro Conference on Real-Time Systems (ECRTS 2017). Leibniz International Proceedings in Informatics (LIPIcs), Volume 76, pp. 12:1-12:22, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2017)

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@InProceedings{joshi_et_al:LIPIcs.ECRTS.2017.12,
  author =	{Joshi, Prachi and Zeng, Haibo and Bordoloi, Unmesh D. and Samii, Soheil and Ravi, S. S. and Shukla, Sandeep K.},
  title =	{{The Multi-Domain Frame Packing Problem for CAN-FD}},
  booktitle =	{29th Euromicro Conference on Real-Time Systems (ECRTS 2017)},
  pages =	{12:1--12:22},
  series =	{Leibniz International Proceedings in Informatics (LIPIcs)},
  ISBN =	{978-3-95977-037-8},
  ISSN =	{1868-8969},
  year =	{2017},
  volume =	{76},
  editor =	{Bertogna, Marko},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2017.12},
  URN =		{urn:nbn:de:0030-drops-71551},
  doi =		{10.4230/LIPIcs.ECRTS.2017.12},
  annote =	{Keywords: Frame Packing, CAN-FD, Integer Linear Programming, Audsley's Algorithm}
}
Document
DOI: 10.4230/DagSemProc.07041.6
Complexity of Scheduling in Synthesizing Hardware from Concurrent Action Oriented Specifications

Authors: Gaurav Singh, S. S. Ravi, Sumit Ahuja, and Sandeep Shukla

Published in: Dagstuhl Seminar Proceedings, Volume 7041, Power-aware Computing Systems (2007)

Abstract
Concurrent Action Oriented Specifications (CAOS) formalism such as Bluespec Inc.'s Bluespec System Verilog (BSV) has been recently shown to be effective for hardware modeling and synthesis. This formalism offers the benefits of automatic handling of concurrency issues in highly concurrent system descriptions, and the associated synthesis algorithms have been shown to produce efficient hardware comparable to those generated from hand-written Verilog/VHDL. These benefits which are inherent in such a synthesis process also aid in faster architectural exploration. This is because CAOS allows a high-level description (above RTL) of a design in terms of atomic transactions, where each transaction corresponds to a collection of operations. Optimal scheduling of such actions in CAOS-based synthesis process is crucial in order to generate hardware that is efficient in terms of area, latency and power. In this paper, we analyze the complexity of the scheduling problems associated with CAOS-based synthesis and discuss several heuristics for meeting the peak power goals of designs generated from CAOS. We also discuss approximability of these problems as appropriate.
Cite as

Gaurav Singh, S. S. Ravi, Sumit Ahuja, and Sandeep Shukla. Complexity of Scheduling in Synthesizing Hardware from Concurrent Action Oriented Specifications. In Power-aware Computing Systems. Dagstuhl Seminar Proceedings, Volume 7041, pp. 1-25, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2007)

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@InProceedings{singh_et_al:DagSemProc.07041.6,
  author =	{Singh, Gaurav and Ravi, S. S. and Ahuja, Sumit and Shukla, Sandeep},
  title =	{{Complexity of Scheduling in Synthesizing Hardware from Concurrent Action Oriented Specifications}},
  booktitle =	{Power-aware Computing Systems},
  pages =	{1--25},
  series =	{Dagstuhl Seminar Proceedings (DagSemProc)},
  ISSN =	{1862-4405},
  year =	{2007},
  volume =	{7041},
  editor =	{Luca Benini and Naehyuck Chang and Ulrich Kremer and Christian W. Probst},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/DagSemProc.07041.6},
  URN =		{urn:nbn:de:0030-drops-11055},
  doi =		{10.4230/DagSemProc.07041.6},
  annote =	{Keywords: Hardware Synthesis, Concurrent Action Oriented Specifications (CAOS), Scheduling, Complexity, Peak Power.}
}

Ravi, Srivatsan

Document
DOI: 10.4230/LIPIcs.AFT.2025.29
Efficient Parallel Execution of Blockchain Transactions Leveraging Conflict Specifications

Authors: Parwat Singh Anjana, Matin Amini, Rohit Kapoor, Rahul Parmar, Raghavendra Ramesh, Srivatsan Ravi, and Joshua Tobkin

Published in: LIPIcs, Volume 354, 7th Conference on Advances in Financial Technologies (AFT 2025)

Abstract
Parallel execution of smart contract transactions in large multicore architectures is critical for higher efficiency and improved throughput. The main bottleneck for maximizing the throughput of a node through parallel execution is transaction conflict resolution: when two transactions interact with the same data, like an account balance, their order matters. Imagine one transaction sends tokens from account A to account B, and another tries to send tokens from account B to account C. If the second transaction happens before the first one, the token balance in account B might be wrong, causing the entire system to break. Conflicts like these must be managed carefully, or you end up with an inconsistent, unusable blockchain state. Traditional software transactional memory (STM) has been identified as a possible abstraction for the concurrent execution of transactions within a block, with Block-STM pioneering its application for efficient blockchain transaction processing on multicore validator nodes. This paper presents a parallel execution methodology that leverages conflict specification information of the transactions for block transactional memory (BTM) algorithms. Our experimental analysis, conducted over synthetic transactional workloads and real-world blocks, demonstrates that BTMs leveraging conflict specifications outperform their plain counterparts on both EVM and MoveVM. Our proposed BTM implementations achieve up to 1.75× speedup over sequential execution and outperform the state-of-the-art Parallel-EVM (PEVM) execution by up to 1.33× across synthetic workloads.
Cite as

Parwat Singh Anjana, Matin Amini, Rohit Kapoor, Rahul Parmar, Raghavendra Ramesh, Srivatsan Ravi, and Joshua Tobkin. Efficient Parallel Execution of Blockchain Transactions Leveraging Conflict Specifications. In 7th Conference on Advances in Financial Technologies (AFT 2025). Leibniz International Proceedings in Informatics (LIPIcs), Volume 354, pp. 29:1-29:26, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2025)

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@InProceedings{anjana_et_al:LIPIcs.AFT.2025.29,
  author =	{Anjana, Parwat Singh and Amini, Matin and Kapoor, Rohit and Parmar, Rahul and Ramesh, Raghavendra and Ravi, Srivatsan and Tobkin, Joshua},
  title =	{{Efficient Parallel Execution of Blockchain Transactions Leveraging Conflict Specifications}},
  booktitle =	{7th Conference on Advances in Financial Technologies (AFT 2025)},
  pages =	{29:1--29:26},
  series =	{Leibniz International Proceedings in Informatics (LIPIcs)},
  ISBN =	{978-3-95977-400-0},
  ISSN =	{1868-8969},
  year =	{2025},
  volume =	{354},
  editor =	{Avarikioti, Zeta and Christin, Nicolas},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/LIPIcs.AFT.2025.29},
  URN =		{urn:nbn:de:0030-drops-247485},
  doi =		{10.4230/LIPIcs.AFT.2025.29},
  annote =	{Keywords: Blockchain, Smart Contract, Parallel Execution, Conflict Specifications}
}
Document
DOI: 10.4230/LIPIcs.DISC.2017.9
Cost of Concurrency in Hybrid Transactional Memory

Authors: Trevor Brown and Srivatsan Ravi

Published in: LIPIcs, Volume 91, 31st International Symposium on Distributed Computing (DISC 2017)

Abstract
State-of-the-art software transactional memory (STM) implementations achieve good performance by carefully avoiding the overhead of incremental validation (i.e., re-reading previously read data items to avoid inconsistency) while still providing progressiveness (allowing transactional aborts only due to data conflicts). Hardware transactional memory (HTM) implementations promise even better performance, but offer no progress guarantees. Thus, they must be combined with STMs, leading to hybrid TMs (HyTMs) in which hardware transactions must be instrumented (i.e., access metadata) to detect contention with software transactions. We show that, unlike in progressive STMs, software transactions in progressive HyTMs cannot avoid incremental validation. In fact, this result holds even if hardware transactions can read metadata non-speculatively. We then present opaque HyTM algorithms providing progressiveness for a subset of transactions that are optimal in terms of hardware instrumentation. We explore the concurrency vs. hardware instrumentation vs. software validation trade-offs for these algorithms. Our experiments with Intel and IBM POWER8 HTMs seem to suggest that (i) the cost of concurrency also exists in practice, (ii) it is important to implement HyTMs that provide progressiveness for a maximal set of transactions without incurring high hardware instrumentation overhead or using global contending bottlenecks and (iii) there is no easy way to derive more efficient HyTMs by taking advantage of non-speculative accesses within hardware.
Cite as

Trevor Brown and Srivatsan Ravi. Cost of Concurrency in Hybrid Transactional Memory. In 31st International Symposium on Distributed Computing (DISC 2017). Leibniz International Proceedings in Informatics (LIPIcs), Volume 91, pp. 9:1-9:16, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2017)

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@InProceedings{brown_et_al:LIPIcs.DISC.2017.9,
  author =	{Brown, Trevor and Ravi, Srivatsan},
  title =	{{Cost of Concurrency in Hybrid Transactional Memory}},
  booktitle =	{31st International Symposium on Distributed Computing (DISC 2017)},
  pages =	{9:1--9:16},
  series =	{Leibniz International Proceedings in Informatics (LIPIcs)},
  ISBN =	{978-3-95977-053-8},
  ISSN =	{1868-8969},
  year =	{2017},
  volume =	{91},
  editor =	{Richa, Andr\'{e}a},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/LIPIcs.DISC.2017.9},
  URN =		{urn:nbn:de:0030-drops-79958},
  doi =		{10.4230/LIPIcs.DISC.2017.9},
  annote =	{Keywords: Transactional memory, Lower bounds, Opacity}
}
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