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DOI: 10.4230/OASIcs.WCET.2007.1189

A Framework for Static Analysis of VHDL Code

Authors: Marc Schlickling and Markus Pister

Published in: OASIcs, Volume 6, 7th International Workshop on Worst-Case Execution Time Analysis (WCET'07) (2007)

Abstract

Software in real time systems underlies strict timing constraints. These are among others hard deadlines regarding the worst-case execution time (WCET) of the application. Thus, the computation of a safe and precise WCET is a key issue1 for validating the behavior of safety-critical systems, e.g. the flight control system in avionics or the airbag control software in the automotive industry. Saarland University and AbsInt Angewandte Informatik GmbH have developed a successful approach for computing the WCET of a task. The resulting tool, called aiT, is based on the abstract interpretation [3, 4] of timing models of the processor and its periphery. Such timing models are hand-crafted and therefore error-prone. Additionally the modeling requires a hard engineering effort, so that the development process is very time consuming. Because modern processors are synthesized from a formal hardware specification, e.g., in VHDL or VERILOG, the hand-crafted timing model can be developed by manually analyzing the processor specification. Due to the complexity of this step, there is a need for support tools that ease the creation of analyzes on such specifi- cations. This paper introduces the primer work on a framework for static analyzes on VHDL.

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Marc Schlickling and Markus Pister. A Framework for Static Analysis of VHDL Code. In 7th International Workshop on Worst-Case Execution Time Analysis (WCET'07). Open Access Series in Informatics (OASIcs), Volume 6, pp. 1-6, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2007)

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@InProceedings{schlickling_et_al:OASIcs.WCET.2007.1189,
  author =	{Schlickling, Marc and Pister, Markus},
  title =	{{A Framework for Static Analysis of VHDL Code}},
  booktitle =	{7th International Workshop on Worst-Case Execution Time Analysis (WCET'07)},
  pages =	{1--6},
  series =	{Open Access Series in Informatics (OASIcs)},
  ISBN =	{978-3-939897-05-7},
  ISSN =	{2190-6807},
  year =	{2007},
  volume =	{6},
  editor =	{Rochange, Christine},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.WCET.2007.1189},
  URN =		{urn:nbn:de:0030-drops-11891},
  doi =		{10.4230/OASIcs.WCET.2007.1189},
  annote =	{Keywords: Timing Analysis, Worst-Case Execution Time, VHDL, Static Analysis}
}

Document

DOI: 10.4230/DagSemProc.05451.3

05451 Group 5 – Bananas, Dark Worlds, and AspectH

Authors: Silvia Breu, Marc Schlickling, and Nuno Miguel Feixa Rodrigues

Published in: Dagstuhl Seminar Proceedings, Volume 5451, Beyond Program Slicing (2006)

Abstract

This report summarises our idea of code clone detection in Haskell code and refactorings based on identified clones as it evolved in our working group-of-three discussion at the Dagstuhl seminar "Beyond Program Slicing".

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Silvia Breu, Marc Schlickling, and Nuno Miguel Feixa Rodrigues. 05451 Group 5 – Bananas, Dark Worlds, and AspectH. In Beyond Program Slicing. Dagstuhl Seminar Proceedings, Volume 5451, pp. 1-8, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2006)

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@InProceedings{breu_et_al:DagSemProc.05451.3,
  author =	{Breu, Silvia and Schlickling, Marc and Rodrigues, Nuno Miguel Feixa},
  title =	{{05451 Group 5 – Bananas, Dark Worlds, and AspectH}},
  booktitle =	{Beyond Program Slicing},
  pages =	{1--8},
  series =	{Dagstuhl Seminar Proceedings (DagSemProc)},
  ISSN =	{1862-4405},
  year =	{2006},
  volume =	{5451},
  editor =	{David W. Binkley and Mark Harman and Jens Krinke},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/DagSemProc.05451.3},
  URN =		{urn:nbn:de:0030-drops-4910},
  doi =		{10.4230/DagSemProc.05451.3},
  annote =	{Keywords: Haskell, code clone detection, refactoring, functional control graph}
}

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Documents authored by Schlickling, Marc

A Framework for Static Analysis of VHDL Code

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05451 Group 5 – Bananas, Dark Worlds, and AspectH

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