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Documents authored by Stoico, Vincenzo

Document
Technical Track Paper
DOI: 10.4230/LIPIcs.ESEM.2026.30
Beyond Response Time: Investigating the Power Behavior of Performance Antipatterns

Authors: Alessandro Aneggi, Vincenzo Stoico, and Andrea Janes

Published in: LIPIcs, Volume 394, 20th International Symposium on Empirical Software Engineering and Measurement (ESEM 2026)

Abstract
Background. Performance antipatterns are well known for degrading the responsiveness of microservice-based systems. However, although their impact on latency has been widely studied, their relationship with energy consumption remains largely unexplored. Aims. This study empirically investigates whether ten widely recognized performance antipatterns, as defined by Smith and Williams, affect power consumption and energy-related behavior in containerized environments. Method. We implemented ten antipatterns as isolated containerized services and evaluated them under controlled load conditions. For each antipattern, we conducted 30 repeated runs and collected measurements of response time, CPU and DRAM power consumption, and resource utilization. Results. While all injected antipatterns degraded performance as expected, only a subset showed a statistically significant positive relationship between increased response time and higher power consumption. Some antipatterns exhibited a clear association between performance degradation and increased power demand. In contrast, others reached CPU saturation early, such that power draw remained nearly constant despite rising response times. In these cases, additional slowdowns primarily increased total execution time rather than instantaneous power demand. Conclusions. Performance antipatterns do not affect power and energy-related behavior uniformly. This study provides a systematic foundation for characterizing how different performance flaws are associated with power and energy-related behavior, offering actionable insights for architects aiming to design more energy-aware software systems.
Cite as

Alessandro Aneggi, Vincenzo Stoico, and Andrea Janes. Beyond Response Time: Investigating the Power Behavior of Performance Antipatterns. In 20th International Symposium on Empirical Software Engineering and Measurement (ESEM 2026). Leibniz International Proceedings in Informatics (LIPIcs), Volume 394, pp. 30:1-30:20, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2026)

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@InProceedings{aneggi_et_al:LIPIcs.ESEM.2026.30,
  author =	{Aneggi, Alessandro and Stoico, Vincenzo and Janes, Andrea},
  title =	{{Beyond Response Time: Investigating the Power Behavior of Performance Antipatterns}},
  booktitle =	{20th International Symposium on Empirical Software Engineering and Measurement (ESEM 2026)},
  pages =	{30:1--30:20},
  series =	{Leibniz International Proceedings in Informatics (LIPIcs)},
  ISBN =	{978-3-95977-450-5},
  ISSN =	{1868-8969},
  year =	{2026},
  volume =	{394},
  editor =	{Feldt, Robert and Paasivaara, Maria and Mendez, Daniel and Wagner, Stefan and Bar\'{o}n, Marvin Mu\~{n}oz},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/LIPIcs.ESEM.2026.30},
  URN =		{urn:nbn:de:0030-drops-279987},
  doi =		{10.4230/LIPIcs.ESEM.2026.30},
  annote =	{Keywords: performance antipatterns, microservices, power consumption, energy consumption, energy efficiency}
}
Artifact
Software
DOI: 10.4230/artifacts.22912
SLIDE-x (System-Level Infrastructure for HW/SW Dataset E-xtraction)

Authors: Vittoriano Muttillo and Vincenzo Stoico

Abstract
Cite as

Vittoriano Muttillo, Vincenzo Stoico. SLIDE-x (System-Level Infrastructure for HW/SW Dataset E-xtraction) (Software, Source Code). Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2025)

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@misc{dagstuhl-artifact-22912,
   title = {{SLIDE-x (System-Level Infrastructure for HW/SW Dataset E-xtraction)}}, 
   author = {Muttillo, Vittoriano and Stoico, Vincenzo},
   note = {Software, version 1.0., AIDOaRt grant agreement No. 10100735, MATISSE grant agreement No. 101140216, swhId: \href{https://archive.softwareheritage.org/swh:1:rev:0907cf39f7d023d0dc2e8307e1ffef6115d0377a;origin=https://github.com/hepsycode/SLIDE-x;visit=swh:1:snp:d73c612114afc6dff6a86a042fa006576440f5ec}{\texttt{swh:1:rev:0907cf39f7d023d0dc2e8307e1ffef6115d0377a}} (visited on 2025-02-27)},
   url = {https://github.com/hepsycode/SLIDE-x},
   doi = {10.4230/artifacts.22912},
}
Document
DOI: 10.4230/OASIcs.PARMA-DITAM.2025.3
System-Level Timing Performance Estimation Based on a Unifying HW/SW Performance Metric

Authors: Vittoriano Muttillo, Vincenzo Stoico, Giacomo Valente, Marco Santic, Luigi Pomante, and Daniele Frigioni

Published in: OASIcs, Volume 127, 16th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 14th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms (PARMA-DITAM 2025)

Abstract
The rapidly increasing complexity of embedded systems and the critical impact of non-functional requirements demand the adoption of an appropriate system-level HW/SW co-design methodology. This methodology tries to satisfy all design requirements by simultaneously considering several alternative HW/SW implementations. In this context, early performance estimation approaches are crucial in reducing the design space, thereby minimizing design time and cost. To address the challenge of system-level performance estimation, this work presents and formalizes a novel approach based on a unifying HW/SW performance metric for early execution time estimation. The proposed approach estimates the execution time of a C function when executed by different HW/SW processor technologies. The approach is validated through an extensive experimental study, demonstrating its effectiveness and efficiency in terms of estimation error (i.e., lower than 10%) and estimation time (close to zero) when compared to existing methods in the literature.
Cite as

Vittoriano Muttillo, Vincenzo Stoico, Giacomo Valente, Marco Santic, Luigi Pomante, and Daniele Frigioni. System-Level Timing Performance Estimation Based on a Unifying HW/SW Performance Metric. In 16th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 14th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms (PARMA-DITAM 2025). Open Access Series in Informatics (OASIcs), Volume 127, pp. 3:1-3:14, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2025)

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@InProceedings{muttillo_et_al:OASIcs.PARMA-DITAM.2025.3,
  author =	{Muttillo, Vittoriano and Stoico, Vincenzo and Valente, Giacomo and Santic, Marco and Pomante, Luigi and Frigioni, Daniele},
  title =	{{System-Level Timing Performance Estimation Based on a Unifying HW/SW Performance Metric}},
  booktitle =	{16th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 14th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms (PARMA-DITAM 2025)},
  pages =	{3:1--3:14},
  series =	{Open Access Series in Informatics (OASIcs)},
  ISBN =	{978-3-95977-363-8},
  ISSN =	{2190-6807},
  year =	{2025},
  volume =	{127},
  editor =	{Cattaneo, Daniele and Fazio, Maria and Kosmidis, Leonidas and Morabito, Gabriele},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.PARMA-DITAM.2025.3},
  URN =		{urn:nbn:de:0030-drops-229071},
  doi =		{10.4230/OASIcs.PARMA-DITAM.2025.3},
  annote =	{Keywords: embedded systems, hw/sw co-design, performance estimation, lasso, machine learning}
}

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