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Documents authored by Yomsi, Patrick Meumeu

Document
Complete Volume
DOI: 10.4230/OASIcs.NG-RES.2024
OASIcs, Volume 117, NG-RES 2024, Complete Volume

Authors: Patrick Meumeu Yomsi and Stefan Wildermann

Published in: OASIcs, Volume 117, Fifth Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2024)

Abstract
OASIcs, Volume 117, NG-RES 2024, Complete Volume
Cite as

Fifth Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2024). Open Access Series in Informatics (OASIcs), Volume 117, pp. 1-62, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2024)

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@Proceedings{yomsi_et_al:OASIcs.NG-RES.2024,
  title =	{{OASIcs, Volume 117, NG-RES 2024, Complete Volume}},
  booktitle =	{Fifth Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2024)},
  pages =	{1--62},
  series =	{Open Access Series in Informatics (OASIcs)},
  ISBN =	{978-3-95977-313-3},
  ISSN =	{2190-6807},
  year =	{2024},
  volume =	{117},
  editor =	{Yomsi, Patrick Meumeu and Wildermann, Stefan},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.NG-RES.2024},
  URN =		{urn:nbn:de:0030-drops-197028},
  doi =		{10.4230/OASIcs.NG-RES.2024},
  annote =	{Keywords: OASIcs, Volume 117, NG-RES 2024, Complete Volume}
}
Document
Front Matter
DOI: 10.4230/OASIcs.NG-RES.2024.0
Front Matter, Table of Contents, Preface, Conference Organization

Authors: Patrick Meumeu Yomsi and Stefan Wildermann

Published in: OASIcs, Volume 117, Fifth Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2024)

Abstract
Front Matter, Table of Contents, Preface, Conference Organization
Cite as

Fifth Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2024). Open Access Series in Informatics (OASIcs), Volume 117, pp. 0:i-0:x, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2024)

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@InProceedings{yomsi_et_al:OASIcs.NG-RES.2024.0,
  author =	{Yomsi, Patrick Meumeu and Wildermann, Stefan},
  title =	{{Front Matter, Table of Contents, Preface, Conference Organization}},
  booktitle =	{Fifth Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2024)},
  pages =	{0:i--0:x},
  series =	{Open Access Series in Informatics (OASIcs)},
  ISBN =	{978-3-95977-313-3},
  ISSN =	{2190-6807},
  year =	{2024},
  volume =	{117},
  editor =	{Yomsi, Patrick Meumeu and Wildermann, Stefan},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.NG-RES.2024.0},
  URN =		{urn:nbn:de:0030-drops-197032},
  doi =		{10.4230/OASIcs.NG-RES.2024.0},
  annote =	{Keywords: Front Matter, Table of Contents, Preface, Conference Organization}
}
Document
DOI: 10.4230/OASIcs.NG-RES.2021.2
EDF Scheduling and Minimal-Overlap Shortest-Path Routing for Real-Time TSCH Networks

Authors: Miguel Gutiérrez Gaitán, Luís Almeida, Pedro Miguel Santos, and Patrick Meumeu Yomsi

Published in: OASIcs, Volume 87, Second Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2021)

Abstract
With the scope of Industry 4.0 and the Industrial Internet of Things (IIoT), wireless technologies have gained momentum in the industrial realm. Wireless standards such as WirelessHART, ISA100.11a, IEEE 802.15.4e and 6TiSCH are among the most popular, given their suitability to support real-time data traffic in wireless sensor and actuator networks (WSAN). Theoretical and empirical studies have covered prioritized packet scheduling in extenso, but only little has been done concerning methods that enhance and/or guarantee real-time performance based on routing decisions. In this work, we propose a greedy heuristic to reduce overlap in shortest-path routing for WSANs with packet transmissions scheduled under the earliest-deadline-first (EDF) policy. We evaluated our approach under varying network configurations and observed remarkable dominance in terms of the number of overlaps, transmission conflicts, and schedulability, regardless of the network workload and connectivity. We further observe that well-known graph network parameters, e.g., vertex degree, density, betweenness centrality, etc., have a special influence on the path overlaps, and thus provide useful insights to improve the real-time performance of the network.
Cite as

Miguel Gutiérrez Gaitán, Luís Almeida, Pedro Miguel Santos, and Patrick Meumeu Yomsi. EDF Scheduling and Minimal-Overlap Shortest-Path Routing for Real-Time TSCH Networks. In Second Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2021). Open Access Series in Informatics (OASIcs), Volume 87, pp. 2:1-2:12, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2021)

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@InProceedings{gaitan_et_al:OASIcs.NG-RES.2021.2,
  author =	{Gait\'{a}n, Miguel Guti\'{e}rrez and Almeida, Lu{\'\i}s and Santos, Pedro Miguel and Yomsi, Patrick Meumeu},
  title =	{{EDF Scheduling and Minimal-Overlap Shortest-Path Routing for Real-Time TSCH Networks}},
  booktitle =	{Second Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2021)},
  pages =	{2:1--2:12},
  series =	{Open Access Series in Informatics (OASIcs)},
  ISBN =	{978-3-95977-178-8},
  ISSN =	{2190-6807},
  year =	{2021},
  volume =	{87},
  editor =	{Bertogna, Marko and Terraneo, Federico},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.NG-RES.2021.2},
  URN =		{urn:nbn:de:0030-drops-134786},
  doi =		{10.4230/OASIcs.NG-RES.2021.2},
  annote =	{Keywords: Real-time communication, Routing, Scheduling, TDMA, Wireless networks}
}
Document
DOI: 10.4230/OASIcs.WCET.2017.10
The P-SOCRATES Timing Analysis Methodology for Parallel Real-Time Applications Deployed on Many-Core Platforms

Authors: Vincent Nelis, Patrick Meumeu Yomsi, and Luís Miguel Pinho

Published in: OASIcs, Volume 57, 17th International Workshop on Worst-Case Execution Time Analysis (WCET 2017)

Abstract
This paper presents the timing analysis methodology developed in the European project P-SOCRATES (Parallel Software Framework for Time-Critical Many-core Systems). This timing analysis methodology is defined for parallel applications that must satisfy both performance and real-time requirements and are executed on modern many-core processor architectures. We discuss the motivation and objectives of the project, the timing analysis flow that we proposed, the tool that has been developed to automatize it, and finally we report on some of the preliminary results that we have obtained when applying this methodology to the three application use-cases of the project.
Cite as

Vincent Nelis, Patrick Meumeu Yomsi, and Luís Miguel Pinho. The P-SOCRATES Timing Analysis Methodology for Parallel Real-Time Applications Deployed on Many-Core Platforms. In 17th International Workshop on Worst-Case Execution Time Analysis (WCET 2017). Open Access Series in Informatics (OASIcs), Volume 57, pp. 10:1-10:9, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2017)

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@InProceedings{nelis_et_al:OASIcs.WCET.2017.10,
  author =	{Nelis, Vincent and Yomsi, Patrick Meumeu and Pinho, Lu{\'\i}s Miguel},
  title =	{{The P-SOCRATES Timing Analysis Methodology for Parallel Real-Time Applications Deployed on Many-Core Platforms}},
  booktitle =	{17th International Workshop on Worst-Case Execution Time Analysis (WCET 2017)},
  pages =	{10:1--10:9},
  series =	{Open Access Series in Informatics (OASIcs)},
  ISBN =	{978-3-95977-057-6},
  ISSN =	{2190-6807},
  year =	{2017},
  volume =	{57},
  editor =	{Reineke, Jan},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.WCET.2017.10},
  URN =		{urn:nbn:de:0030-drops-73120},
  doi =		{10.4230/OASIcs.WCET.2017.10},
  annote =	{Keywords: Timing analysis, many-core platform}
}
Document
DOI: 10.4230/OASIcs.WCET.2016.6
The Variability of Application Execution Times on a Multi-Core Platform

Authors: Vincent Nélis, Patrick Meumeu Yomsi, and Luís Miguel Pinho

Published in: OASIcs, Volume 55, 16th International Workshop on Worst-Case Execution Time Analysis (WCET 2016)

Abstract
It is a known fact that processes running concurrently on different cores in a multicore environment interfere with each other on the processor shared resources. The contention on these shared resources considerably slows down the execution on every core since sometimes the cores must stall while their requests to access the resources are being served. But by how much the execution may be slowed down due to this interference? In this paper we answer this question with numbers coming from experimentation. That is, we quantify the magnitude of the impact of the interference on the execution time by running programs taken from the TACLeBench benchmark suite, a popular benchmark suite in the real-time research community, on the first generation of Kalray manycore processor family, the MPPA-256 (the development board) that goes by the codename "Andey".
Cite as

Vincent Nélis, Patrick Meumeu Yomsi, and Luís Miguel Pinho. The Variability of Application Execution Times on a Multi-Core Platform. In 16th International Workshop on Worst-Case Execution Time Analysis (WCET 2016). Open Access Series in Informatics (OASIcs), Volume 55, pp. 6:1-6:11, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2016)

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@InProceedings{nelis_et_al:OASIcs.WCET.2016.6,
  author =	{N\'{e}lis, Vincent and Yomsi, Patrick Meumeu and Pinho, Lu{\'\i}s Miguel},
  title =	{{The Variability of Application Execution Times on a Multi-Core Platform}},
  booktitle =	{16th International Workshop on Worst-Case Execution Time Analysis (WCET 2016)},
  pages =	{6:1--6:11},
  series =	{Open Access Series in Informatics (OASIcs)},
  ISBN =	{978-3-95977-025-5},
  ISSN =	{2190-6807},
  year =	{2016},
  volume =	{55},
  editor =	{Schoeberl, Martin},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.WCET.2016.6},
  URN =		{urn:nbn:de:0030-drops-68994},
  doi =		{10.4230/OASIcs.WCET.2016.6},
  annote =	{Keywords: Execution time variability, timing analysis, WCET estimates, multi-cores, many-cores}
}
Document
DOI: 10.4230/OASIcs.WCET.2014.63
The Challenge of Time-Predictability in Modern Many-Core Architectures

Authors: Vincent Nélis, Patrick Meumeu Yomsi, Luís Miguel Pinho, José Carlos Fonseca, Marko Bertogna, Eduardo Quiñones, Roberto Vargas, and Andrea Marongiu

Published in: OASIcs, Volume 39, 14th International Workshop on Worst-Case Execution Time Analysis (2014)

Abstract
The recent technological advancements and market trends are causing an interesting phenomenon towards the convergence of High-Performance Computing (HPC) and Embedded Computing (EC) domains. Many recent HPC applications require huge amounts of information to be processed within a bounded amount of time while EC systems are increasingly concerned with providing higher performance in real-time. The convergence of these two domains towards systems requiring both high performance and a predictable time-behavior challenges the capabilities of current hardware architectures. Fortunately, the advent of next-generation many-core embedded platforms has the chance of intercepting this converging need for predictability and high-performance, allowing HPC and EC applications to be executed on efficient and powerful heterogeneous architectures integrating general-purpose processors with many-core computing fabrics. However, addressing this mixed set of requirements is not without its own challenges and it is now of paramount importance to develop new techniques to exploit the massively parallel computation capabilities of many-core platforms in a predictable way.
Cite as

Vincent Nélis, Patrick Meumeu Yomsi, Luís Miguel Pinho, José Carlos Fonseca, Marko Bertogna, Eduardo Quiñones, Roberto Vargas, and Andrea Marongiu. The Challenge of Time-Predictability in Modern Many-Core Architectures. In 14th International Workshop on Worst-Case Execution Time Analysis. Open Access Series in Informatics (OASIcs), Volume 39, pp. 63-72, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2014)

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@InProceedings{nelis_et_al:OASIcs.WCET.2014.63,
  author =	{N\'{e}lis, Vincent and Yomsi, Patrick Meumeu and Pinho, Lu{\'\i}s Miguel and Fonseca, Jos\'{e} Carlos and Bertogna, Marko and Qui\~{n}ones, Eduardo and Vargas, Roberto and Marongiu, Andrea},
  title =	{{The Challenge of Time-Predictability in Modern Many-Core Architectures}},
  booktitle =	{14th International Workshop on Worst-Case Execution Time Analysis},
  pages =	{63--72},
  series =	{Open Access Series in Informatics (OASIcs)},
  ISBN =	{978-3-939897-69-9},
  ISSN =	{2190-6807},
  year =	{2014},
  volume =	{39},
  editor =	{Falk, Heiko},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.WCET.2014.63},
  URN =		{urn:nbn:de:0030-drops-46050},
  doi =		{10.4230/OASIcs.WCET.2014.63},
  annote =	{Keywords: Time-Predictability, Many-Cores, Multi-Cores, Timing Analysis}
}
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