Published in: LIPIcs, Volume 287, 15th Innovations in Theoretical Computer Science Conference (ITCS 2024)
Ce Jin, R. Ryan Williams, and Nathaniel Young. A VLSI Circuit Model Accounting for Wire Delay. In 15th Innovations in Theoretical Computer Science Conference (ITCS 2024). Leibniz International Proceedings in Informatics (LIPIcs), Volume 287, pp. 66:1-66:22, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2024)
@InProceedings{jin_et_al:LIPIcs.ITCS.2024.66, author = {Jin, Ce and Williams, R. Ryan and Young, Nathaniel}, title = {{A VLSI Circuit Model Accounting for Wire Delay}}, booktitle = {15th Innovations in Theoretical Computer Science Conference (ITCS 2024)}, pages = {66:1--66:22}, series = {Leibniz International Proceedings in Informatics (LIPIcs)}, ISBN = {978-3-95977-309-6}, ISSN = {1868-8969}, year = {2024}, volume = {287}, editor = {Guruswami, Venkatesan}, publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik}, address = {Dagstuhl, Germany}, URL = {https://drops.dagstuhl.de/entities/document/10.4230/LIPIcs.ITCS.2024.66}, URN = {urn:nbn:de:0030-drops-195949}, doi = {10.4230/LIPIcs.ITCS.2024.66}, annote = {Keywords: circuit complexity, systolic arrays, VLSI, wire delay} }