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Leibniz Transactions on Embedded Systems, Volume 5, Issue 1
LITES, Volume 5, Issue 1
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LITES, Volume 5
Journal: Leibniz Transactions on Embedded Systems (LITES)
Publication Details
- published at: 2018-05-30
- Publisher: Schloss Dagstuhl – Leibniz-Zentrum für Informatik
- DBLP: db/journals/lites/lites5
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Complete Issue
LITES, Volume 5, Issue 1
Abstract
LITES, Volume 5, Issue 1
Cite as
LITES, Volume 5, Issue 1, pp. 1-134, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2018)
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@Article{LITES-v005-i001,
title = {{LITES, Volume 5, Issue 1}},
journal = {Leibniz Transactions on Embedded Systems},
pages = {1--134},
ISSN = {2199-2002},
year = {2018},
volume = {5},
number = {1},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/LITES-v005-i001},
doi = {10.4230/LITES-v005-i001},
annote = {Keywords: LITES, Volume 5, Issue 1}
}
Document
Risk-Aware Scheduling of Dual Criticality Job Systems Using Demand Distributions
Abstract
We pose the problem of scheduling Mixed Criticality (MC) job systems when there are only two criticality levels, Lo and Hi -referred to as Dual Criticality job systems- on a single processing platform, when job demands are probabilistic and their distributions are known. The current MC models require that the scheduling policy allocate as little execution time as possible to Lo-criticality jobs if the scenario of execution is of Hi criticality, and drop Lo-criticality jobs entirely as soon as the execution scenario's criticality level can be inferred and is Hi. The work incurred by "incorrectly" scheduling Lo-criticality jobs in cases of Hi realized scenarios might affect the feasibility of Hi criticality jobs; we quantify this work and call it Work Threatening Feasibility (WTF). Our objective is to construct online scheduling policies that minimize the expected WTF for the given instance, and under which the instance is feasible in a probabilistic sense that is consistent with the traditional deterministic definition of MC feasibility. We develop a probabilistic framework for MC scheduling, where feasibility is defined in terms of (chance) constraints on the probabilities that Lo and Hi jobs meet their deadlines. The probabilities are computed over the set of sample paths, or trajectories, induced by executing the policy, and those paths are dependent upon the set of execution scenarios and the given demand distributions. Our goal is to exploit the information provided by job distributions to compute the minimum expected WTF below which the given instance is not feasible in probability, and to compute a (randomized) "efficiently implementable" scheduling policy that realizes the latter quantity. We model the problem as a Constrained Markov Decision Process (CMDP) over a suitable state space and a finite planning horizon, and show that an optimal (non-stationary) Markov randomized scheduling policy exists. We derive an optimal policy by solving a Linear Program (LP). We also carry out quantitative evaluations on select probabilistic MC instances to demonstrate that our approach potentially outperforms current MC scheduling policies.
Cite as
Bader Naim Alahmad and Sathish Gopalakrishnan. Risk-Aware Scheduling of Dual Criticality Job Systems Using Demand Distributions. In LITES, Volume 5, Issue 1 (2018). Leibniz Transactions on Embedded Systems, Volume 5, Issue 1, pp. 01:1-01:30, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2018)
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@Article{alahmad_et_al:LITES-v005-i001-a001,
author = {Alahmad, Bader Naim and Gopalakrishnan, Sathish},
title = {{Risk-Aware Scheduling of Dual Criticality Job Systems Using Demand Distributions}},
journal = {Leibniz Transactions on Embedded Systems},
pages = {01:1--01:30},
ISSN = {2199-2002},
year = {2018},
volume = {5},
number = {1},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/LITES-v005-i001-a001},
URN = {urn:nbn:de:0030-drops-192720},
doi = {10.4230/LITES-v005-i001-a001},
annote = {Keywords: Mixed criticalities, Probability distribution, Real time systems, Scheduling, Chance constrained Markov decision process, Linear programming, Randomized policy}
}
Document
Errata for Three Papers (2004-05) on Fixed-Priority Scheduling with Self-Suspensions
Abstract
The purpose of this article is to (i) highlight the flaws in three previously published works [Audsley, 2004a; Audsley, 2004b; Bletsas, 2005] on the worst-case response time analysis for tasks with self-suspensions and (ii) provide straightforward fixes for those flaws, hence rendering the analysis safe.
Cite as
Konstantinos Bletsas, Neil C. Audsley, Wen-Hung Huang, Jian-Jia Chen, and Geoffrey Nelissen. Errata for Three Papers (2004-05) on Fixed-Priority Scheduling with Self-Suspensions. In LITES, Volume 5, Issue 1 (2018). Leibniz Transactions on Embedded Systems, Volume 5, Issue 1, pp. 02:1-02:20, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2018)
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@Article{bletsas_et_al:LITES-v005-i001-a002,
author = {Bletsas, Konstantinos and Audsley, Neil C. and Huang, Wen-Hung and Chen, Jian-Jia and Nelissen, Geoffrey},
title = {{Errata for Three Papers (2004-05) on Fixed-Priority Scheduling with Self-Suspensions}},
journal = {Leibniz Transactions on Embedded Systems},
pages = {02:1--02:20},
ISSN = {2199-2002},
year = {2018},
volume = {5},
number = {1},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/LITES-v005-i001-a002},
URN = {urn:nbn:de:0030-drops-192736},
doi = {10.4230/LITES-v005-i001-a002},
annote = {Keywords: real-time, scheduling, self-suspension, worst-case response time analysis}
}
Document
The Semantic Foundations and a Landscape of Cache-Persistence Analyses
Abstract
We clarify the notion of cache persistence and contribute to the understanding of persistence analysis for caches with least-recently-used replacement.To this end, we provide the first formal definition of persistence as a property of a trace semantics. Based on this trace semantics we introduce a semantics-based, i.e., abstract-interpretation-based persistence analysis framework.We identify four basic persistence analyses and prove their correctness as instances of this analysis framework.Combining these basic persistence analyses via two generic cooperation mechanisms yields a lattice of ten persistence analyses.Notably, this lattice contains all persistence analyses previously described in the literature. As a consequence, we obtain uniform correctness proofs for all prior analyses and a precise understanding of how and why these analyses work, as well as how they relate to each other in terms of precision.
Cite as
Jan Reineke. The Semantic Foundations and a Landscape of Cache-Persistence Analyses. In LITES, Volume 5, Issue 1 (2018). Leibniz Transactions on Embedded Systems, Volume 5, Issue 1, pp. 03:1-03:52, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2018)
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@Article{reineke:LITES-v005-i001-a003,
author = {Reineke, Jan},
title = {{The Semantic Foundations and a Landscape of Cache-Persistence Analyses}},
journal = {Leibniz Transactions on Embedded Systems},
pages = {03:1--03:52},
ISSN = {2199-2002},
year = {2018},
volume = {5},
number = {1},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/LITES-v005-i001-a003},
URN = {urn:nbn:de:0030-drops-192748},
doi = {10.4230/LITES-v005-i001-a003},
annote = {Keywords: caches, persistence analysis, WCET analysis}
}
Document
A Static Analysis for the Minimization of Voters in Fault-Tolerant Circuits
Abstract
We present a formal approach to minimize the number of voters in triple-modular redundant (TMR) sequential circuits. Our technique actually works on a single copy of the TMR circuit and considers a large class of fault mo dels of the form “at most 1 Single-Event Upset (SEU) or Single-Event Transient (SET) every k clock cycles”. Verification-based voter minimization guarantees that the resulting TMR circuit (i) is fault tolerant to the soft-errors defined by the fault model and (ii) is functionally equivalent to the initial TMR circuit. Our approach operates at the logic level and takes into account the input and output interface specifications of the circuit. Its implementation makes use of graph traversal algorithms, fixed-point iterations, and binary decision diagrams (BDD). Experimental results on the ITC’99 benchmark suite indicate that our method significantly decreases the number of inserted voters, yielding a hardware reduction of up to 55% and a clock frequency increase of up to 35% compared to full TMR. As our experiments show, if the SEU fault-model is replaced with the stricter fault-model of SET, it has a minor impact on the number of removed voters. On the other hand, BDD-based modelling of SET effects represents a more complex task than the modelling of an SEU as a bit-flip. We propose solutions for this task and explain the nature of encountered problems. We address scalability issues arising from formal verification with approximations and assess their efficiency and precision.
Cite as
Dmitry Burlyaev, Pascal Fradet, and Alain Girault. A Static Analysis for the Minimization of Voters in Fault-Tolerant Circuits. In LITES, Volume 5, Issue 1 (2018). Leibniz Transactions on Embedded Systems, Volume 5, Issue 1, pp. 04:1-04:26, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2018)
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@Article{burlyaev_et_al:LITES-v005-i001-a004,
author = {Burlyaev, Dmitry and Fradet, Pascal and Girault, Alain},
title = {{A Static Analysis for the Minimization of Voters in Fault-Tolerant Circuits}},
journal = {Leibniz Transactions on Embedded Systems},
pages = {04:1--04:26},
ISSN = {2199-2002},
year = {2018},
volume = {5},
number = {1},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/LITES-v005-i001-a004},
URN = {urn:nbn:de:0030-drops-192753},
doi = {10.4230/LITES-v005-i001-a004},
annote = {Keywords: Digital Circuits, Fault-tolerance, Optimization, Static Analysis, Triple Modular Redundancy}
}