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Documents authored by Hardy, Damien

Document
DOI: 10.4230/OASIcs.WCET.2017.8
The Heptane Static Worst-Case Execution Time Estimation Tool

Authors: Damien Hardy, Benjamin Rouxel, and Isabelle Puaut

Published in: OASIcs, Volume 57, 17th International Workshop on Worst-Case Execution Time Analysis (WCET 2017)

Abstract
Estimation of worst-case execution times (WCETs) is required to validate the temporal behavior of hard real time systems. Heptane is an open-source software program that estimates upper bounds of execution times on MIPS and ARM v7 architectures, offered to the WCET estimation community to experiment new WCET estimation techniques. The software architecture of Heptane was designed to be as modular and extensible as possible to facilitate the integration of new approaches. This paper is devoted to a description of Heptane, and includes information on the analyses it implements, how to use it and extend it.
Cite as

Damien Hardy, Benjamin Rouxel, and Isabelle Puaut. The Heptane Static Worst-Case Execution Time Estimation Tool. In 17th International Workshop on Worst-Case Execution Time Analysis (WCET 2017). Open Access Series in Informatics (OASIcs), Volume 57, pp. 8:1-8:12, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2017)

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@InProceedings{hardy_et_al:OASIcs.WCET.2017.8,
  author =	{Hardy, Damien and Rouxel, Benjamin and Puaut, Isabelle},
  title =	{{The Heptane Static Worst-Case Execution Time Estimation Tool}},
  booktitle =	{17th International Workshop on Worst-Case Execution Time Analysis (WCET 2017)},
  pages =	{8:1--8:12},
  series =	{Open Access Series in Informatics (OASIcs)},
  ISBN =	{978-3-95977-057-6},
  ISSN =	{2190-6807},
  year =	{2017},
  volume =	{57},
  editor =	{Reineke, Jan},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.WCET.2017.8},
  URN =		{urn:nbn:de:0030-drops-73033},
  doi =		{10.4230/OASIcs.WCET.2017.8},
  annote =	{Keywords: Worst-Case Execution Time Estimation, Static Analysis, WCET Estimation Tool, Implicit Path Enumeration Technique}
}
Document
DOI: 10.4230/LIPIcs.ECRTS.2017.14
Cache-Conscious Offline Real-Time Task Scheduling for Multi-Core Processors

Authors: Viet Anh Nguyen, Damien Hardy, and Isabelle Puaut

Published in: LIPIcs, Volume 76, 29th Euromicro Conference on Real-Time Systems (ECRTS 2017)

Abstract
Most schedulability analysis techniques for multi-core architectures assume a single Worst-Case Execution Time (WCET) per task, which is valid in all execution conditions. This assumption is too pessimistic for parallel applications running on multi-core architectures with local instruction or data caches, for which the WCET of a task depends on the cache contents at the beginning of its execution, itself depending on the task that was executed before the task under study. In this paper, we propose two scheduling techniques for multi-core architectures equipped with local instruction and data caches. The two techniques schedule a parallel application modeled as a task graph, and generate a static partitioned non-preemptive schedule. We propose an optimal method, using an Integer Linear Programming (ILP) formulation, as well as a heuristic method based on list scheduling. Experimental results show that by taking into account the effect of private caches on tasks' WCETs, the length of generated schedules is significantly reduced as compared to schedules generated by cache-unaware scheduling methods. The observed schedule length reduction on streaming applications is 11% on average for the optimal method and 9% on average for the heuristic method.
Cite as

Viet Anh Nguyen, Damien Hardy, and Isabelle Puaut. Cache-Conscious Offline Real-Time Task Scheduling for Multi-Core Processors. In 29th Euromicro Conference on Real-Time Systems (ECRTS 2017). Leibniz International Proceedings in Informatics (LIPIcs), Volume 76, pp. 14:1-14:22, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2017)

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@InProceedings{nguyen_et_al:LIPIcs.ECRTS.2017.14,
  author =	{Nguyen, Viet Anh and Hardy, Damien and Puaut, Isabelle},
  title =	{{Cache-Conscious Offline Real-Time Task Scheduling for Multi-Core Processors}},
  booktitle =	{29th Euromicro Conference on Real-Time Systems (ECRTS 2017)},
  pages =	{14:1--14:22},
  series =	{Leibniz International Proceedings in Informatics (LIPIcs)},
  ISBN =	{978-3-95977-037-8},
  ISSN =	{1868-8969},
  year =	{2017},
  volume =	{76},
  editor =	{Bertogna, Marko},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2017.14},
  URN =		{urn:nbn:de:0030-drops-71642},
  doi =		{10.4230/LIPIcs.ECRTS.2017.14},
  annote =	{Keywords: Real-time scheduling, Cache-conscious scheduling, Many-core architectures, ILP, Static list scheduling}
}
Document
DOI: 10.4230/OASIcs.WCET.2009.2283
WCET Analysis of Multi-Level Set-Associative Data Caches

Authors: Benjamin Lesage, Damien Hardy, and Isabelle Puaut

Published in: OASIcs, Volume 10, 9th International Workshop on Worst-Case Execution Time Analysis (WCET'09) (2009)

Abstract
Nowadays, the presence of cache hierarchies tends to be a common trend in processor architectures, even in hardware for real-time embedded systems. Caches are used to fill the gap between the processor and the main memory, reducing access times based on spatial and temporal locality properties of tasks. Cache hierarchies are going even further however at the price of increased complexity. In this paper, we present a safe static data cache analysis method for hierarchies of non-inclusive caches. Using this method, we show that considering the cache hierarchy in the context of data caches allows tighter estimates of the worst case execution time than when considering only the first cache level. We also present considerations about the update policy for data caches.
Cite as

Benjamin Lesage, Damien Hardy, and Isabelle Puaut. WCET Analysis of Multi-Level Set-Associative Data Caches. In 9th International Workshop on Worst-Case Execution Time Analysis (WCET'09). Open Access Series in Informatics (OASIcs), Volume 10, pp. 1-12, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2009)

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@InProceedings{lesage_et_al:OASIcs.WCET.2009.2283,
  author =	{Lesage, Benjamin and Hardy, Damien and Puaut, Isabelle},
  title =	{{WCET Analysis of Multi-Level Set-Associative Data Caches}},
  booktitle =	{9th International Workshop on Worst-Case Execution Time Analysis (WCET'09)},
  pages =	{1--12},
  series =	{Open Access Series in Informatics (OASIcs)},
  ISBN =	{978-3-939897-14-9},
  ISSN =	{2190-6807},
  year =	{2009},
  volume =	{10},
  editor =	{Holsti, Niklas},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.WCET.2009.2283},
  URN =		{urn:nbn:de:0030-drops-22837},
  doi =		{10.4230/OASIcs.WCET.2009.2283},
  annote =	{Keywords: WCET analysis, data cache, multi-level, set-associative}
}
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