Published in: OASIcs, Volume 127, 16th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 14th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms (PARMA-DITAM 2025)
Vittoriano Muttillo, Vincenzo Stoico, Giacomo Valente, Marco Santic, Luigi Pomante, and Daniele Frigioni. System-Level Timing Performance Estimation Based on a Unifying HW/SW Performance Metric. In 16th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 14th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms (PARMA-DITAM 2025). Open Access Series in Informatics (OASIcs), Volume 127, pp. 3:1-3:14, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2025)
@InProceedings{muttillo_et_al:OASIcs.PARMA-DITAM.2025.3, author = {Muttillo, Vittoriano and Stoico, Vincenzo and Valente, Giacomo and Santic, Marco and Pomante, Luigi and Frigioni, Daniele}, title = {{System-Level Timing Performance Estimation Based on a Unifying HW/SW Performance Metric}}, booktitle = {16th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 14th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms (PARMA-DITAM 2025)}, pages = {3:1--3:14}, series = {Open Access Series in Informatics (OASIcs)}, ISBN = {978-3-95977-363-8}, ISSN = {2190-6807}, year = {2025}, volume = {127}, editor = {Cattaneo, Daniele and Fazio, Maria and Kosmidis, Leonidas and Morabito, Gabriele}, publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik}, address = {Dagstuhl, Germany}, URL = {https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.PARMA-DITAM.2025.3}, URN = {urn:nbn:de:0030-drops-229071}, doi = {10.4230/OASIcs.PARMA-DITAM.2025.3}, annote = {Keywords: embedded systems, hw/sw co-design, performance estimation, lasso, machine learning} }
Published in: OASIcs, Volume 121, 22nd International Workshop on Worst-Case Execution Time Analysis (WCET 2024)
Gianluca Brilli, Giacomo Valente, Alessandro Capotondi, Tania Di Mascio, and Andrea Marongiu. Invited Paper: On the Granularity of Bandwidth Regulation in FPGA-Based Heterogeneous Systems on Chip. In 22nd International Workshop on Worst-Case Execution Time Analysis (WCET 2024). Open Access Series in Informatics (OASIcs), Volume 121, pp. 5:1-5:11, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2024)
@InProceedings{brilli_et_al:OASIcs.WCET.2024.5, author = {Brilli, Gianluca and Valente, Giacomo and Capotondi, Alessandro and Di Mascio, Tania and Marongiu, Andrea}, title = {{Invited Paper: On the Granularity of Bandwidth Regulation in FPGA-Based Heterogeneous Systems on Chip}}, booktitle = {22nd International Workshop on Worst-Case Execution Time Analysis (WCET 2024)}, pages = {5:1--5:11}, series = {Open Access Series in Informatics (OASIcs)}, ISBN = {978-3-95977-346-1}, ISSN = {2190-6807}, year = {2024}, volume = {121}, editor = {Carle, Thomas}, publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik}, address = {Dagstuhl, Germany}, URL = {https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.WCET.2024.5}, URN = {urn:nbn:de:0030-drops-204732}, doi = {10.4230/OASIcs.WCET.2024.5}, annote = {Keywords: Bandwidth Regulation, System-on-Chip, FPGA} }
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