18 Search Results for "Teich, Jürgen"


Document
History-Based Run-Time Requirement Enforcement of Non-Functional Properties on MPSoCs

Authors: Khalil Esper and Jürgen Teich

Published in: OASIcs, Volume 117, Fifth Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2024)


Abstract
Embedded system applications usually have requirements regarding non-functional properties of their execution like latency or power consumption. Enforcement of such requirements can be implemented by a reactive control loop, where an enforcer determines based on a system response (feedback) how to control the system, e.g., by selecting the number of active cores allocated to a program or by scaling their voltage/frequency mode. It is of a particular interest to design enforcement strategies for which it is possible to provide formal guarantees with respect to requirement violations, especially under a largely varying environmental input (workload) per execution. In this paper, we consider enforcement strategies that are modeled by a finite state machine (FSM) and the environment by a discrete-time Markov chain. Such a formalization enables the formal verification of temporal properties (verification goals) regarding the satisfaction of requirements of a given enforcement strategy. In this paper, we propose history-based enforcement FSMs which compute a reaction not just on the current, but on a fixed history of K previously observed system responses. We then analyze the quality of such enforcement FSMs in terms of the probability of satisfying a given set of verification goals and compare them to enforcement FSMs that react solely on the current system response. As experimental results, we present three use cases while considering requirements on latency and power consumption. The results show that history-based enforcement FSMs outperform enforcement FSMs that only consider the current system response regarding the probability of satisfying a given set of verification goals.

Cite as

Khalil Esper and Jürgen Teich. History-Based Run-Time Requirement Enforcement of Non-Functional Properties on MPSoCs. In Fifth Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2024). Open Access Series in Informatics (OASIcs), Volume 117, pp. 4:1-4:11, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2024)


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@InProceedings{esper_et_al:OASIcs.NG-RES.2024.4,
  author =	{Esper, Khalil and Teich, J\"{u}rgen},
  title =	{{History-Based Run-Time Requirement Enforcement of Non-Functional Properties on MPSoCs}},
  booktitle =	{Fifth Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2024)},
  pages =	{4:1--4:11},
  series =	{Open Access Series in Informatics (OASIcs)},
  ISBN =	{978-3-95977-313-3},
  ISSN =	{2190-6807},
  year =	{2024},
  volume =	{117},
  editor =	{Yomsi, Patrick Meumeu and Wildermann, Stefan},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.NG-RES.2024.4},
  URN =		{urn:nbn:de:0030-drops-197074},
  doi =		{10.4230/OASIcs.NG-RES.2024.4},
  annote =	{Keywords: Verification, Runtime Requirement Enforcement, History, Latency}
}
Document
Throughput and Memory Optimization for Parallel Implementations of Dataflow Networks Using Multi-Reader Buffers

Authors: Martin Letras, Joachim Falk, and Jürgen Teich

Published in: OASIcs, Volume 108, Fourth Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2023)


Abstract
In this paper, we introduce the concept of Multi-Reader Buffers (MRBs) for high throughput and memory-efficient implementation of dataflow applications. Our work is motivated by the huge amount of data that needs to be processed and typically accessed in a FIFO manner, particularly in image and video processing applications. Here, multi-cast, fork, and merge operator implementations known today produce huge memory overheads by storing and communicating copies of the same data. As a remedy, we first introduce MRBs as buffers preserving FIFO semantics for a finite number of readers of the same data while storing each data item only once. Second, we present an approach for memory minimization of data flow networks by replacing all multi-cast actors and connected FIFOs with MRBs. Third, we present a Design Space Exploration approach to selectively replace multi-cast actors with MRBs in order to explore memory, throughput, and processor resource allocation tradeoffs. Our results show that the explored Pareto fronts of our approach improve the solution quality over a reference by 78% in average for six benchmark applications in terms of a hypervolume indicator.

Cite as

Martin Letras, Joachim Falk, and Jürgen Teich. Throughput and Memory Optimization for Parallel Implementations of Dataflow Networks Using Multi-Reader Buffers. In Fourth Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2023). Open Access Series in Informatics (OASIcs), Volume 108, pp. 6:1-6:13, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2023)


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@InProceedings{letras_et_al:OASIcs.NG-RES.2023.6,
  author =	{Letras, Martin and Falk, Joachim and Teich, J\"{u}rgen},
  title =	{{Throughput and Memory Optimization for Parallel Implementations of Dataflow Networks Using Multi-Reader Buffers}},
  booktitle =	{Fourth Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2023)},
  pages =	{6:1--6:13},
  series =	{Open Access Series in Informatics (OASIcs)},
  ISBN =	{978-3-95977-268-6},
  ISSN =	{2190-6807},
  year =	{2023},
  volume =	{108},
  editor =	{Terraneo, Federico and Cattaneo, Daniele},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.NG-RES.2023.6},
  URN =		{urn:nbn:de:0030-drops-177374},
  doi =		{10.4230/OASIcs.NG-RES.2023.6},
  annote =	{Keywords: Dataflow, Memory Optimization, MPSoCs, Design Space Exploration}
}
Document
RAVEN: Reinforcement Learning for Generating Verifiable Run-Time Requirement Enforcers for MPSoCs

Authors: Khalil Esper, Jan Spieck, Pierre-Louis Sixdenier, Stefan Wildermann, and Jürgen Teich

Published in: OASIcs, Volume 108, Fourth Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2023)


Abstract
In embedded systems, applications frequently have to meet non-functional requirements regarding, e.g., real-time or energy consumption constraints, when executing on a given MPSoC target platform. Feedback-based controllers have been proposed that react to transient environmental factors by adapting the DVFS settings or degree of parallelism following some predefined control strategy. However, it is, in general, not possible to give formal guarantees for the obtained controllers to satisfy a given set of non-functional requirements. Run-time requirement enforcement has emerged as a field of research for the enforcement of non-functional requirements at run-time, allowing to define and formally verify properties on respective control strategies specified by automata. However, techniques for the automatic generation of such controllers have not yet been established. In this paper, we propose a technique using reinforcement learning to automatically generate verifiable feedback-based enforcers. For that, we train a control policy based on a representative input sequence at design time. The learned control strategy is then transformed into a verifiable enforcement automaton which constitutes our run-time control model that can handle unseen input data. As a case study, we apply the approach to generate controllers that are able to increase the probability of satisfying a given set of requirement verification goals compared to multiple state-of-the-art approaches, as can be verified by model checkers.

Cite as

Khalil Esper, Jan Spieck, Pierre-Louis Sixdenier, Stefan Wildermann, and Jürgen Teich. RAVEN: Reinforcement Learning for Generating Verifiable Run-Time Requirement Enforcers for MPSoCs. In Fourth Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2023). Open Access Series in Informatics (OASIcs), Volume 108, pp. 7:1-7:16, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2023)


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@InProceedings{esper_et_al:OASIcs.NG-RES.2023.7,
  author =	{Esper, Khalil and Spieck, Jan and Sixdenier, Pierre-Louis and Wildermann, Stefan and Teich, J\"{u}rgen},
  title =	{{RAVEN: Reinforcement Learning for Generating Verifiable Run-Time Requirement Enforcers for MPSoCs}},
  booktitle =	{Fourth Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2023)},
  pages =	{7:1--7:16},
  series =	{Open Access Series in Informatics (OASIcs)},
  ISBN =	{978-3-95977-268-6},
  ISSN =	{2190-6807},
  year =	{2023},
  volume =	{108},
  editor =	{Terraneo, Federico and Cattaneo, Daniele},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.NG-RES.2023.7},
  URN =		{urn:nbn:de:0030-drops-177380},
  doi =		{10.4230/OASIcs.NG-RES.2023.7},
  annote =	{Keywords: Verification, Runtime Requirement Enforcement, Reinforcement Learning}
}
Document
Multi-Requirement Enforcement of Non-Functional Properties on MPSoCs Using Enforcement FSMs - A Case Study

Authors: Khalil Esper, Stefan Wildermann, and Jürgen Teich

Published in: OASIcs, Volume 98, Third Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2022)


Abstract
Embedded system applications usually have to meet real-time, energy or safety requirements on programs typically concurrently executed on a given MPSoC target platform. Enforcing such properties, e.g., by adapting the number of processors allocated to a program or by scaling the voltage/frequency mode of involved processors, is a difficult problem to solve, especially with a typically large varying environmental input (workload) per execution. In a previous work [Esper et al., 2021], we formalized the related enforcement problem using (a) finite state machines to model enforcement strategies, (b) discrete-time Markov chains to model the uncertain environment determining the system’s workload, and (c) the system response that defines the feedback for the reactive enforcer. In this paper, we apply that approach to specify and verify multi-requirement enforcement strategies and assess a case study for enforcing two independent requirements at the same time, i.e., latency and energy consumption. We evaluate and compare different enforcement strategies using probabilistic verification for the use case of an object detection application.

Cite as

Khalil Esper, Stefan Wildermann, and Jürgen Teich. Multi-Requirement Enforcement of Non-Functional Properties on MPSoCs Using Enforcement FSMs - A Case Study. In Third Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2022). Open Access Series in Informatics (OASIcs), Volume 98, pp. 2:1-2:13, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2022)


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@InProceedings{esper_et_al:OASIcs.NG-RES.2022.2,
  author =	{Esper, Khalil and Wildermann, Stefan and Teich, J\"{u}rgen},
  title =	{{Multi-Requirement Enforcement of Non-Functional Properties on MPSoCs Using Enforcement FSMs - A Case Study}},
  booktitle =	{Third Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2022)},
  pages =	{2:1--2:13},
  series =	{Open Access Series in Informatics (OASIcs)},
  ISBN =	{978-3-95977-221-1},
  ISSN =	{2190-6807},
  year =	{2022},
  volume =	{98},
  editor =	{Bertogna, Marko and Terraneo, Federico and Reghenzani, Federico},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.NG-RES.2022.2},
  URN =		{urn:nbn:de:0030-drops-161102},
  doi =		{10.4230/OASIcs.NG-RES.2022.2},
  annote =	{Keywords: Runtime Requirement Enforcement, Verification, Finite State Machine, Markov Chain, Energy Consumption, Probabilistic Model Cheking, PCTL, MPSoC}
}
Document
Invited Paper
A Comparative Evaluation of Latency-Aware Energy Optimization Approaches in Many-Core Systems (Invited Paper)

Authors: Khalil Esper, Stefan Wildermann, and Jürgen Teich

Published in: OASIcs, Volume 87, Second Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2021)


Abstract
Many applications vary a lot in execution time depending on their workload. A prominent example is image processing applications, where the execution time is dependent on the content or the size of the processed input images. An interesting case is when these applications have quality-of-service requirements such as soft deadlines, that they should meet as good as possible. A further complicated case is when such applications have one or even multiple further objectives to optimize like, e.g., energy consumption. Approaches that dynamically adapt the processing resources to application needs under multiple optimization goals and constraints can be characterized into the application-specific and feedback-based techniques. Whereas application-specific approaches typically statically use an offline stage to determine the best configuration for each known workload, feedback-based approaches, using, e.g., control theory, adapt the system without the need of knowing the effect of workload on these goals. In this paper, we evaluate a state-of-the-art approach of each of the two categories and compare them for image processing applications in terms of energy consumption and number of deadline misses on a given many-core architecture. In addition, we propose a second feedback-based approach that is based on finite state machines (FSMs). The obtained results suggest that whereas the state-of-the-art application-specific approach is able to meet a specified latency deadline whenever possible while consuming the least amount of energy, it requires a perfect characterization of the workload on a given many-core system. If such knowledge is not available, the feedback-based approaches have their strengths in achieving comparable energy savings, but missing deadlines more often.

Cite as

Khalil Esper, Stefan Wildermann, and Jürgen Teich. A Comparative Evaluation of Latency-Aware Energy Optimization Approaches in Many-Core Systems (Invited Paper). In Second Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2021). Open Access Series in Informatics (OASIcs), Volume 87, pp. 1:1-1:12, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2021)


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@InProceedings{esper_et_al:OASIcs.NG-RES.2021.1,
  author =	{Esper, Khalil and Wildermann, Stefan and Teich, J\"{u}rgen},
  title =	{{A Comparative Evaluation of Latency-Aware Energy Optimization Approaches in Many-Core Systems}},
  booktitle =	{Second Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2021)},
  pages =	{1:1--1:12},
  series =	{Open Access Series in Informatics (OASIcs)},
  ISBN =	{978-3-95977-178-8},
  ISSN =	{2190-6807},
  year =	{2021},
  volume =	{87},
  editor =	{Bertogna, Marko and Terraneo, Federico},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.NG-RES.2021.1},
  URN =		{urn:nbn:de:0030-drops-134779},
  doi =		{10.4230/OASIcs.NG-RES.2021.1},
  annote =	{Keywords: energy optimization, control-theory, timing analysis, soft real-time, dynamic voltage and frequency scaling, finite state machines, multi-core, many-core}
}
Document
Energy Minimization in DAG Scheduling on MPSoCs at Run-Time: Theory and Practice

Authors: Bertrand Simon, Joachim Falk, Nicole Megow, and Jürgen Teich

Published in: OASIcs, Volume 77, Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2020)


Abstract
Static (offline) techniques for mapping applications given by task graphs to MPSoC systems often deliver overly pessimistic and thus suboptimal results w.r.t. exploiting time slack in order to minimize the energy consumption. This holds true in particular in case computation times of tasks may be workload-dependent and becoming known only at runtime or in case of conditionally executed tasks or scenarios. This paper studies and quantitatively evaluates different classes of algorithms for scheduling periodic applications given by task graphs (i.e., DAGs) with precedence constraints and a global deadline on homogeneous MPSoCs purely at runtime on a per-instance base. We present and analyze algorithms providing provably optimal results as well as approximation algorithms with proven guarantees on the achieved energy savings. For problem instances taken from realistic embedded system benchmarks as well as synthetic scalable problems, we provide results on the computation time and quality of each algorithm to perform a) scheduling and b) voltage/speed assignments for each task at runtime. In our portfolio, we distinguish as well continuous and discrete speed (e.g., DVFS-related) assignment problems. In summary, the presented ties between theory (algorithmic complexity and optimality) and execution time analysis deliver important insights on the practical usability of the presented algorithms for runtime optimization of task scheduling and speed assignment on MPSoCs.

Cite as

Bertrand Simon, Joachim Falk, Nicole Megow, and Jürgen Teich. Energy Minimization in DAG Scheduling on MPSoCs at Run-Time: Theory and Practice. In Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2020). Open Access Series in Informatics (OASIcs), Volume 77, pp. 2:1-2:13, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2020)


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@InProceedings{simon_et_al:OASIcs.NG-RES.2020.2,
  author =	{Simon, Bertrand and Falk, Joachim and Megow, Nicole and Teich, J\"{u}rgen},
  title =	{{Energy Minimization in DAG Scheduling on MPSoCs at Run-Time: Theory and Practice}},
  booktitle =	{Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2020)},
  pages =	{2:1--2:13},
  series =	{Open Access Series in Informatics (OASIcs)},
  ISBN =	{978-3-95977-136-8},
  ISSN =	{2190-6807},
  year =	{2020},
  volume =	{77},
  editor =	{Bertogna, Marko and Terraneo, Federico},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.NG-RES.2020.2},
  URN =		{urn:nbn:de:0030-drops-117781},
  doi =		{10.4230/OASIcs.NG-RES.2020.2},
  annote =	{Keywords: energy minimization, speed scaling, precedence graphs, scheduling, critical path, MPSoC}
}
Document
Real-Time Task Migration for Dynamic Resource Management in Many-Core Systems

Authors: Behnaz Pourmohseni, Fedor Smirnov, Stefan Wildermann, and Jürgen Teich

Published in: OASIcs, Volume 77, Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2020)


Abstract
Dynamic resource management strategies in embedded many-core systems rely on task migration to adapt the deployment (mapping) of applications dynamically, e.g., for thermal/power management or load balancing. In case of hard real-time applications, however, the current practice of on-line application adaptation is limited to reconfiguring the whole application between a set of statically computed mappings with statically verified timing guarantees. This heavily restricts the application’s adaptability. To enable hard real-time task migrations in many-core systems without relying on a static analysis, this paper presents (i) a predictable task migration mechanism supported with (ii) a lightweight migration timing analysis and (iii) a lightweight migration timing feasibility check which can be applied on-line to bound on the worst-case temporal overhead of a migration and examine the admissibility of this overhead w.r.t. the hard real-time requirements of the application. For a variety of applications and many-core platforms, we experimentally demonstrate the feasibility of hard real-time task migrations, the lightness of the proposed timing analysis and feasibility check for on-line use, and the advantage of the proposed task migration approach over mapping reconfiguration as the state-of-the-art real-time adaptation approach for many-core systems.

Cite as

Behnaz Pourmohseni, Fedor Smirnov, Stefan Wildermann, and Jürgen Teich. Real-Time Task Migration for Dynamic Resource Management in Many-Core Systems. In Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2020). Open Access Series in Informatics (OASIcs), Volume 77, pp. 5:1-5:14, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2020)


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@InProceedings{pourmohseni_et_al:OASIcs.NG-RES.2020.5,
  author =	{Pourmohseni, Behnaz and Smirnov, Fedor and Wildermann, Stefan and Teich, J\"{u}rgen},
  title =	{{Real-Time Task Migration for Dynamic Resource Management in Many-Core Systems}},
  booktitle =	{Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2020)},
  pages =	{5:1--5:14},
  series =	{Open Access Series in Informatics (OASIcs)},
  ISBN =	{978-3-95977-136-8},
  ISSN =	{2190-6807},
  year =	{2020},
  volume =	{77},
  editor =	{Bertogna, Marko and Terraneo, Federico},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.NG-RES.2020.5},
  URN =		{urn:nbn:de:0030-drops-117816},
  doi =		{10.4230/OASIcs.NG-RES.2020.5},
  annote =	{Keywords: Hard real-time, task migration, timing analysis, dynamic resource management, multi-core, many-core}
}
Document
Isolation-Aware Timing Analysis and Design Space Exploration for Predictable and Composable Many-Core Systems

Authors: Behnaz Pourmohseni, Fedor Smirnov, Stefan Wildermann, and Jürgen Teich

Published in: LIPIcs, Volume 133, 31st Euromicro Conference on Real-Time Systems (ECRTS 2019)


Abstract
Composable many-core systems enable the independent development and analysis of applications which will be executed on a shared platform where the mix of concurrently executed applications may change dynamically at run time. For each individual application, an off-line DSE is performed to compute several mapping alternatives on the platform, offering Pareto-optimal trade-offs in terms of real-time guarantees, resource usage, etc. At run time, one mapping is then chosen to launch the application on demand. In this context, to enable an independent analysis of each individual application at design time, so-called inter-application isolation schemes are applied which specify temporal/spatial isolation policies between applications. State-of-the-art composable many-core systems are developed based on a fixed isolation scheme that is exclusively applied to every resource in every mapping of every application and use a timing analysis tailored to that isolation scheme to derive timing guarantees for each mapping. A fixed isolation scheme, however, heavily restricts the explored space of solutions and can, therefore, lead to suboptimality. Lifting this restriction necessitates a timing analysis that is applicable to mappings with an arbitrary mix of isolation schemes on different resources. To address this issue, in this paper, we (a) present an isolation-aware timing analysis that - unlike existing analyses - can handle multiple isolation schemes in combination within one mapping and delivers safe yet tight timing bounds by identifying and excluding interference scenarios that can never happen under the given combination of isolation schemes. Based on the timing analysis, we (b) present a DSE which explores the choices of isolation scheme per resource within each mapping and uses the proposed timing analysis for timing verification. Experimental results demonstrate that, for a variety of real-time applications and many-core platforms, the proposed approach achieves an improvement of up to 67% in the quality of delivered mappings compared to approaches based on a fixed isolation scheme.

Cite as

Behnaz Pourmohseni, Fedor Smirnov, Stefan Wildermann, and Jürgen Teich. Isolation-Aware Timing Analysis and Design Space Exploration for Predictable and Composable Many-Core Systems. In 31st Euromicro Conference on Real-Time Systems (ECRTS 2019). Leibniz International Proceedings in Informatics (LIPIcs), Volume 133, pp. 12:1-12:24, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2019)


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@InProceedings{pourmohseni_et_al:LIPIcs.ECRTS.2019.12,
  author =	{Pourmohseni, Behnaz and Smirnov, Fedor and Wildermann, Stefan and Teich, J\"{u}rgen},
  title =	{{Isolation-Aware Timing Analysis and Design Space Exploration for Predictable and Composable Many-Core Systems}},
  booktitle =	{31st Euromicro Conference on Real-Time Systems (ECRTS 2019)},
  pages =	{12:1--12:24},
  series =	{Leibniz International Proceedings in Informatics (LIPIcs)},
  ISBN =	{978-3-95977-110-8},
  ISSN =	{1868-8969},
  year =	{2019},
  volume =	{133},
  editor =	{Quinton, Sophie},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2019.12},
  URN =		{urn:nbn:de:0030-drops-107491},
  doi =		{10.4230/LIPIcs.ECRTS.2019.12},
  annote =	{Keywords: Many-core systems, timing analysis, design space exploration (DSE), isolation scheme, predictability, composability}
}
Document
Adaptive Isolation for Predictability and Security (Dagstuhl Seminar 16441)

Authors: Tulika Mitra, Jürgen Teich, and Lothar Thiele

Published in: Dagstuhl Reports, Volume 6, Issue 10 (2017)


Abstract
This report documents the program and the outcomes of Dagstuhl Seminar 16441 "Adaptive Isolation for Predictability and Security". Semiconductor technology is at the verge of integrating hundreds of processor cores on a single device. Indeed, affordable multi-processor system-on-a-chip (MPSoC) technology is becoming available. It is already heavily used for acceleration of applications from domains of graphics, gaming (e.g., GPUs) and high performance computing (e.g., Xeon Phi). The potential of MPSoCs is yet to explode for novel application areas of embedded and cyber-physical systems such as the domains of automotive (e.g., driver assistance systems), industrial automation and avionics where non-functional aspects of program execution must be enforceable. Instead of best-effort and average performance, these real-time applications demand timing predictability and/or security levels specifiable on a per-application basis. Therefore the cross-cutting topics of the seminar were methods for temporal and spatial isolation. These methods were discussed for their capabilities to enforce the above non-functional properties without sacrificing any efficiency or resource utilization. To be able to provide isolation instantaneously, e.g., even for just segments of a program under execution, adaptivity is essential at all hardware- and software layers. Support for adaptivity was the second focal aspect of the seminar. Here, virtualization and new adaptive resource reservation protocols were discussed and analyzed for their capabilities to provide application/job-wise predictable program execution qualities on demand at some costs and overheads. If the overhead can be kept low, there is a chance that adaptive isolation, the title of the seminar, may enable the adoption of MPSoC technology for many new application areas of embedded systems.

Cite as

Tulika Mitra, Jürgen Teich, and Lothar Thiele. Adaptive Isolation for Predictability and Security (Dagstuhl Seminar 16441). In Dagstuhl Reports, Volume 6, Issue 10, pp. 120-153, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2017)


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@Article{mitra_et_al:DagRep.6.10.120,
  author =	{Mitra, Tulika and Teich, J\"{u}rgen and Thiele, Lothar},
  title =	{{Adaptive Isolation for Predictability and Security (Dagstuhl Seminar 16441)}},
  pages =	{120--153},
  journal =	{Dagstuhl Reports},
  ISSN =	{2192-5283},
  year =	{2017},
  volume =	{6},
  number =	{10},
  editor =	{Mitra, Tulika and Teich, J\"{u}rgen and Thiele, Lothar},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/DagRep.6.10.120},
  URN =		{urn:nbn:de:0030-drops-69539},
  doi =		{10.4230/DagRep.6.10.120},
  annote =	{Keywords: Adaptive isolation, Embedded systems, Real-Time systems, Predictability, Security, MPSoC, Parallel computing, Programming models, Timing analysis, Virtualization}
}
Document
10281 Abstracts Collection – Dynamically Reconfigurable Architectures

Authors: Peter M. Athanas, Jürgen Becker, Jürgen Teich, and Ingrid Verbauwhede

Published in: Dagstuhl Seminar Proceedings, Volume 10281, Dynamically Reconfigurable Architectures (2010)


Abstract
From 11.07.10 to 16.07.10, Dagstuhl Seminar 10281 ``Dynamically Reconfigurable Architectures '' was held in Schloss Dagstuhl~--~Leibniz Center for Informatics. During the seminar, several participants presented their current research, and ongoing work and open problems were discussed. Abstracts of the presentations given during the seminar as well as abstracts of seminar results and ideas are put together in this paper. The first section describes the seminar topics and goals in general. Links to extended abstracts or full papers are provided, if available.

Cite as

Peter M. Athanas, Jürgen Becker, Jürgen Teich, and Ingrid Verbauwhede. 10281 Abstracts Collection – Dynamically Reconfigurable Architectures. In Dynamically Reconfigurable Architectures. Dagstuhl Seminar Proceedings, Volume 10281, pp. 1-23, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2010)


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@InProceedings{athanas_et_al:DagSemProc.10281.1,
  author =	{Athanas, Peter M. and Becker, J\"{u}rgen and Teich, J\"{u}rgen and Verbauwhede, Ingrid},
  title =	{{10281 Abstracts Collection – Dynamically Reconfigurable Architectures}},
  booktitle =	{Dynamically Reconfigurable Architectures},
  pages =	{1--23},
  series =	{Dagstuhl Seminar Proceedings (DagSemProc)},
  ISSN =	{1862-4405},
  year =	{2010},
  volume =	{10281},
  editor =	{Peter M. Athanas and J\"{u}rgen Becker and J\"{u}rgen Teich and Ingrid Verbauwhede},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/DagSemProc.10281.1},
  URN =		{urn:nbn:de:0030-drops-28962},
  doi =		{10.4230/DagSemProc.10281.1},
  annote =	{Keywords: Dynamically Run-Time Reconfigurable Computing Architectures, Self- adaptive Systems, Computational Models, Circuit Technologies, System Architecture, Reconfigurable/Adaptive Computing based on Nanotechnologies}
}
Document
10281 Summary – Dynamically Reconfigurable Architectures

Authors: Peter M. Athanas, Jürgen Becker, Jürgen Teich, and Ingrid Verbauwhede

Published in: Dagstuhl Seminar Proceedings, Volume 10281, Dynamically Reconfigurable Architectures (2010)


Abstract
Dynamic and partial reconfiguration of hardware architectures such as FPGAs and coarse grain processing arrays bring an additional level of flexibility in the design of electronic systems by exploiting the possibility of configuring functions on-demand during run-time. When compared to emerging software-programmable Multi-Processor System-on-a-Chip (MPSoC) solutions, they benefit a lot from lower cost, more dedication and fit to a certain problem class as well as power and area efficiency. This has led to many new ways of approaching existing research topics in the area of hardware design and optimization techniques. For example, the possibility of performing adaptation during run-time raises questions in the areas of dynamic control, real-time response, on-line power management and design complexity, since the reconfigurability increases the design space towards infinity.

Cite as

Peter M. Athanas, Jürgen Becker, Jürgen Teich, and Ingrid Verbauwhede. 10281 Summary – Dynamically Reconfigurable Architectures. In Dynamically Reconfigurable Architectures. Dagstuhl Seminar Proceedings, Volume 10281, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2010)


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@InProceedings{athanas_et_al:DagSemProc.10281.2,
  author =	{Athanas, Peter M. and Becker, J\"{u}rgen and Teich, J\"{u}rgen and Verbauwhede, Ingrid},
  title =	{{10281 Summary – Dynamically Reconfigurable Architectures}},
  booktitle =	{Dynamically Reconfigurable Architectures},
  series =	{Dagstuhl Seminar Proceedings (DagSemProc)},
  ISSN =	{1862-4405},
  year =	{2010},
  volume =	{10281},
  editor =	{Peter M. Athanas and J\"{u}rgen Becker and J\"{u}rgen Teich and Ingrid Verbauwhede},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/DagSemProc.10281.2},
  URN =		{urn:nbn:de:0030-drops-28926},
  doi =		{10.4230/DagSemProc.10281.2},
  annote =	{Keywords: Dynamically Run-Time Reconfigurable Computing Architectures, Self- adaptive Systems, Computational Models, Circuit Technologies, System Architecture, CAD Tool Support, Reconfigurable/Adaptive Computing based on Nanotechnologies}
}
Document
New Directions for IP Core Watermarking and Identification

Authors: Daniel Ziener and Jürgen Teich

Published in: Dagstuhl Seminar Proceedings, Volume 10281, Dynamically Reconfigurable Architectures (2010)


Abstract
In this talk, we present watermarking and identification techniques for FPGA IP cores. Unlike most existing watermarking techniques, the focus of our techniques lies on ease of verification, even if the protected cores are embedded into a product. Moreover, we have concentrated on higher abstraction levels for embedding the watermark, particularly at the logic level, where IP cores are distributed as netlist cores. With the presented watermarking methods, it is possible to watermark IP cores at the logic level and identify them with a high likelihood and in a reproducible way in a purchased product from a company that is suspected to have committed IP fraud. The investigated techniques establish the authorship by verification of either an FPGA bitfile or the power consumption of a given FPGA.

Cite as

Daniel Ziener and Jürgen Teich. New Directions for IP Core Watermarking and Identification. In Dynamically Reconfigurable Architectures. Dagstuhl Seminar Proceedings, Volume 10281, pp. 1-13, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2010)


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@InProceedings{ziener_et_al:DagSemProc.10281.10,
  author =	{Ziener, Daniel and Teich, J\"{u}rgen},
  title =	{{New Directions for IP Core Watermarking and Identification}},
  booktitle =	{Dynamically Reconfigurable Architectures},
  pages =	{1--13},
  series =	{Dagstuhl Seminar Proceedings (DagSemProc)},
  ISSN =	{1862-4405},
  year =	{2010},
  volume =	{10281},
  editor =	{Peter M. Athanas and J\"{u}rgen Becker and J\"{u}rgen Teich and Ingrid Verbauwhede},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/DagSemProc.10281.10},
  URN =		{urn:nbn:de:0030-drops-28437},
  doi =		{10.4230/DagSemProc.10281.10},
  annote =	{Keywords: IP protection, IP cores, watermarking}
}
Document
06141 Abstracts Collection – Dynamically Reconfigurable Architectures

Authors: Jürgen Becker, Jürgen Teich, Gordon Brebner, and Peter M. Athanas

Published in: Dagstuhl Seminar Proceedings, Volume 6141, Dynamically Reconfigurable Architectures (2006)


Abstract
From 02.04.06 to 07.04.06, the Dagstuhl Seminar 06141 ``Dynamically Reconfigurable Architectures'' was held in the International Conference and Research Center (IBFI), Schloss Dagstuhl. During the seminar, several participants presented their current research, and ongoing work and open problems were discussed. Abstracts of the presentations given during the seminar as well as abstracts of seminar results and ideas are put together in this paper. The first section describes the seminar topics and goals in general. Links to extended abstracts or full papers are provided, if available.

Cite as

Jürgen Becker, Jürgen Teich, Gordon Brebner, and Peter M. Athanas. 06141 Abstracts Collection – Dynamically Reconfigurable Architectures. In Dynamically Reconfigurable Architectures. Dagstuhl Seminar Proceedings, Volume 6141, pp. 1-26, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2006)


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@InProceedings{becker_et_al:DagSemProc.06141.1,
  author =	{Becker, J\"{u}rgen and Teich, J\"{u}rgen and Brebner, Gordon and Athanas, Peter M.},
  title =	{{06141 Abstracts Collection – Dynamically Reconfigurable Architectures}},
  booktitle =	{Dynamically Reconfigurable Architectures},
  pages =	{1--26},
  series =	{Dagstuhl Seminar Proceedings (DagSemProc)},
  ISSN =	{1862-4405},
  year =	{2006},
  volume =	{6141},
  editor =	{Peter M. Athanas and J\"{u}rgen Becker and Gordon Brebner and J\"{u}rgen Teich},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/DagSemProc.06141.1},
  URN =		{urn:nbn:de:0030-drops-8383},
  doi =		{10.4230/DagSemProc.06141.1},
  annote =	{Keywords: Dynamically run-time reconfigurable computing architectures, adaptive systems, computational models, circuit technologies, system architecture, CAD tool support}
}
Document
06141 Executive Summary – Dynamically Reconfigurable Architectures

Authors: Jürgen Becker, Jürgen Teich, Gordon Brebner, and Peter M. Athanas

Published in: Dagstuhl Seminar Proceedings, Volume 6141, Dynamically Reconfigurable Architectures (2006)


Abstract
Dynamic and partial reconfiguration of hardware architectures such as FPGAs and XPPs brings an additional level of flexibility in the design of electronic systems by exploiting the possibility of configuring functions on-demand during run-time. This has led to many new ways of approaching existing research topics in the area of hardware design and optimization techniques. For example, the possibility of performing adaptation during run-time raises questions in the areas of dynamic control, real-time response, on-line power management and design complexity, since the reconfigurability increases the design space towards infinity. This Dagstuhl Seminar on Reconfigurable Architectures has aimed at raising a few of these topics e.g. on-line placement, pre-routing/on-line routing trade-off, power minimization etc., and also at presenting novel ideas on how to overcome the difficulties introduced in dynamic reconfigurable systems.

Cite as

Jürgen Becker, Jürgen Teich, Gordon Brebner, and Peter M. Athanas. 06141 Executive Summary – Dynamically Reconfigurable Architectures. In Dynamically Reconfigurable Architectures. Dagstuhl Seminar Proceedings, Volume 6141, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2006)


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@InProceedings{becker_et_al:DagSemProc.06141.2,
  author =	{Becker, J\"{u}rgen and Teich, J\"{u}rgen and Brebner, Gordon and Athanas, Peter M.},
  title =	{{06141 Executive Summary – Dynamically Reconfigurable Architectures}},
  booktitle =	{Dynamically Reconfigurable Architectures},
  series =	{Dagstuhl Seminar Proceedings (DagSemProc)},
  ISSN =	{1862-4405},
  year =	{2006},
  volume =	{6141},
  editor =	{Peter M. Athanas and J\"{u}rgen Becker and Gordon Brebner and J\"{u}rgen Teich},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/DagSemProc.06141.2},
  URN =		{urn:nbn:de:0030-drops-8372},
  doi =		{10.4230/DagSemProc.06141.2},
  annote =	{Keywords: Reconfigurable Computing, Reconfigurable Supercomputing, Organic Computing, Dynamic Reconfiguration, Reconfigurable Hardware}
}
Document
Bridging the Gap between Relocatability and Available Technology: The Erlangen Slot Machine

Authors: Diana Göhringer, Mateusz Majer, and Jürgen Teich

Published in: Dagstuhl Seminar Proceedings, Volume 6141, Dynamically Reconfigurable Architectures (2006)


Abstract
We present an FPGA-based reconfigurable platform called Erlangen Slot Machine (ESM). The main advantages of this platform are: First, the possibility for each module to access peripherals independent from its location through a programmable crossbar, and local SRAM banks for individual modules. This physical design eases the implementation of run-time reconfigurable partial modules and enables an unrestricted relocation of modules on the device. We present our two-board ESM implementation and demonstrate a partially reconfigurable video filter application as well as a relocatable computer game including a dedicated inter-module communication scheme.

Cite as

Diana Göhringer, Mateusz Majer, and Jürgen Teich. Bridging the Gap between Relocatability and Available Technology: The Erlangen Slot Machine. In Dynamically Reconfigurable Architectures. Dagstuhl Seminar Proceedings, Volume 6141, pp. 1-11, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2006)


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@InProceedings{gohringer_et_al:DagSemProc.06141.5,
  author =	{G\"{o}hringer, Diana and Majer, Mateusz and Teich, J\"{u}rgen},
  title =	{{Bridging the Gap between Relocatability and Available Technology: The Erlangen Slot Machine}},
  booktitle =	{Dynamically Reconfigurable Architectures},
  pages =	{1--11},
  series =	{Dagstuhl Seminar Proceedings (DagSemProc)},
  ISSN =	{1862-4405},
  year =	{2006},
  volume =	{6141},
  editor =	{Peter M. Athanas and J\"{u}rgen Becker and Gordon Brebner and J\"{u}rgen Teich},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/DagSemProc.06141.5},
  URN =		{urn:nbn:de:0030-drops-7369},
  doi =		{10.4230/DagSemProc.06141.5},
  annote =	{Keywords: FPGA-based reconfigurable platform, inter-module communication, crossbar, video filter demo}
}
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