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Leibniz Transactions on Embedded Systems, Volume 3, Issue 1
LITES, Volume 3, Issue 1
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LITES, Volume 3
Journal: Leibniz Transactions on Embedded Systems (LITES)
Publication Details
- published at: 2016-06-10
- Publisher: Schloss Dagstuhl – Leibniz-Zentrum für Informatik
- DBLP: db/journals/lites/lites3
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Complete Issue
LITES, Volume 3, Issue 1
Abstract
LITES, Volume 3, Issue 1
Cite as
LITES, Volume 3, Issue 1, pp. 1-152, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2016)
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@Article{LITES-v003-i001,
title = {{LITES, Volume 3, Issue 1}},
journal = {Leibniz Transactions on Embedded Systems},
pages = {1--152},
ISSN = {2199-2002},
year = {2016},
volume = {3},
number = {1},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/LITES-v003-i001},
doi = {10.4230/LITES-v003-i001},
annote = {Keywords: LITES, Volume 3, Issue 1}
}
Document
Programming Language Constructs Supporting Fault Tolerance
Abstract
In order to render software viable for highly safety-critical applications, we describe how to incorporate fault tolerance mechanisms into the real-time programming language PEARL. Therefore, we present, classify, evaluate and illustrate known fault tolerance methods for software. We link them together with the requirements of the international standard IEC 61508-3 for functional safety. We contribute PEARL-2020 programming language constructs for fault tolerance methods that need to be implemented by operating systems, and code-snippets as well as libraries for those independent from runtime systems.
Cite as
Christina Houben and Sebastian Houben. Programming Language Constructs Supporting Fault Tolerance. In LITES, Volume 3, Issue 1 (2016). Leibniz Transactions on Embedded Systems, Volume 3, Issue 1, pp. 01:1-01:20, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2016)
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@Article{houben_et_al:LITES-v003-i001-a001,
author = {Houben, Christina and Houben, Sebastian},
title = {{Programming Language Constructs Supporting Fault Tolerance}},
journal = {Leibniz Transactions on Embedded Systems},
pages = {01:1--01:20},
ISSN = {2199-2002},
year = {2016},
volume = {3},
number = {1},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/LITES-v003-i001-a001},
doi = {10.4230/LITES-v003-i001-a001},
annote = {Keywords: Fault tolerance, Functional safety, PEARL, Embedded systems, Software engineering}
}
Document
Real-Time Scheduling on Uni- and Multiprocessors based on Priority Promotions
Abstract
This paper addresses the problem of real-time scheduling of a set of sporadic tasks on uni- and multiprocessor platform based on priority promotion. A new preemptive scheduling algorithm, called Fixed-Priority with Priority Promotion (FPP), is proposed. In FPP scheduling, tasks are executed similar to traditional fixed-priority (FP) scheduling but the priority of some tasks are promoted at fixed time interval (called, promotion point) relative to the release time of each job. A policy called Increase Priority at Deadline Difference (IPDD) to compute the promotion points and promoted priorities for each task is proposed. FPP scheduling prioritizes jobs according to Earliest-Deadline-First (EDF) priority when all tasks' priorities follow IPDD policy.It is known that managing (i.e., inserting and removing) jobs in the ready queue of traditional EDF scheduler is more complex than that of FP scheduler. To avoid such problem in FPP scheduling, a simple data structure and efficient operations to manage jobs in the ready queue are proposed. In addition, techniques for implementing priority promotions with and without the use of a hardware timer are proposed.Finally, an effective scheme to reduce the average number of priority promotions is proposed: if a task set is not schedulable using traditional FP scheduling, then promotion points are assigned only to those tasks that need them to meet the deadlines; otherwise, tasks are assigned traditional fixed priorities without any priority promotion. Empirical investigation shows the effectiveness of the proposed scheme in reducing overhead on uniprocessor and in accepting larger number of task sets in comparison to that of using state-of-the-art global schedulability tests for multiprocessors.
Cite as
Risat Mahmud Pathan. Real-Time Scheduling on Uni- and Multiprocessors based on Priority Promotions. In LITES, Volume 3, Issue 1 (2016). Leibniz Transactions on Embedded Systems, Volume 3, Issue 1, pp. 02:1-02:29, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2016)
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@Article{pathan:LITES-v003-i001-a002,
author = {Pathan, Risat Mahmud},
title = {{Real-Time Scheduling on Uni- and Multiprocessors based on Priority Promotions}},
journal = {Leibniz Transactions on Embedded Systems},
pages = {02:1--02:29},
ISSN = {2199-2002},
year = {2016},
volume = {3},
number = {1},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/LITES-v003-i001-a002},
doi = {10.4230/LITES-v003-i001-a002},
annote = {Keywords: Real-Time Systems, Priority Promotion, Schedulability Analysis, Schedulability Condition}
}
Document
Modeling Power Consumption and Temperature in TLM Models
Abstract
Many techniques and tools exist to estimate the power consumption and the temperature map of a chip. These tools help the hardware designers develop power efficient chips in the presence of temperature constraints. For this task, the application can be ignored or at least abstracted by some high level scenarios; at this stage, the actual embedded software is generally not available yet.However, after the hardware is defined, the embedded software can still have a significant influence on the power consumption; i.e., two implementations of the same application can consume more or less power. Moreover, the actual software power manager ensuring the temperature constraints, usually by acting dynamically on the voltage and frequency, must itself be validated. Validating such power management policy requires a model of both actuators and sensors, hence a closed-loop simulation of the functional model with a non-functional one.In this paper, we present and compare several tools to simulate the power and thermal behavior of a chip together with its functionality. We explore several levels of abstraction and study the impact on the precision of the analysis.
Cite as
Matthieu Moy, Claude Helmstetter, Tayeb Bouhadiba, and Florence Maraninchi. Modeling Power Consumption and Temperature in TLM Models. In LITES, Volume 3, Issue 1 (2016). Leibniz Transactions on Embedded Systems, Volume 3, Issue 1, pp. 03:1-03:29, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2016)
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@Article{moy_et_al:LITES-v003-i001-a003,
author = {Moy, Matthieu and Helmstetter, Claude and Bouhadiba, Tayeb and Maraninchi, Florence},
title = {{Modeling Power Consumption and Temperature in TLM Models}},
journal = {Leibniz Transactions on Embedded Systems},
pages = {03:1--03:29},
ISSN = {2199-2002},
year = {2016},
volume = {3},
number = {1},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/LITES-v003-i001-a003},
doi = {10.4230/LITES-v003-i001-a003},
annote = {Keywords: Power consumption, Temperature control, Virtual prototype, SystemC, Transactional modeling}
}
Document
Optimal Scheduling of Periodic Gang Tasks
Abstract
The gang scheduling of parallel implicit-deadline periodic task systems upon identical multiprocessor platforms is considered. In this scheduling problem, parallel tasks use several processors simultaneously. We propose two DPFAIR (deadline partitioning) algorithms that schedule all jobs in every interval of time delimited by two subsequent deadlines. These algorithms define a static schedule pattern that is stretched at run-time in every interval of the DPFAIR schedule. The first algorithm is based on linear programming and is the first one to be proved optimal for the considered gang scheduling problem. Furthermore, it runs in polynomial time for a fixed number m of processors and an efficient implementation is fully detailed. The second algorithm is an approximation algorithm based on a fixed-priority rule that is competitive under resource augmentation analysis in order to compute an optimal schedule pattern. Precisely, its speedup factor is bounded by (2-1/m). Both algorithms are also evaluated through intensive numerical experiments.
Cite as
Joël Goossens and Pascal Richard. Optimal Scheduling of Periodic Gang Tasks. In LITES, Volume 3, Issue 1 (2016). Leibniz Transactions on Embedded Systems, Volume 3, Issue 1, pp. 04:1-04:18, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2016)
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@Article{goossens_et_al:LITES-v003-i001-a004,
author = {Goossens, Jo\"{e}l and Richard, Pascal},
title = {{Optimal Scheduling of Periodic Gang Tasks}},
journal = {Leibniz Transactions on Embedded Systems},
pages = {04:1--04:18},
ISSN = {2199-2002},
year = {2016},
volume = {3},
number = {1},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/LITES-v003-i001-a004},
doi = {10.4230/LITES-v003-i001-a004},
annote = {Keywords: Real-time systems, Scheduling, Parallel tasks}
}
Document
A Survey on Static Cache Analysis for Real-Time Systems
Abstract
Real-time systems are reactive computer systems that must produce their reaction to a stimulus within given time bounds. A vital verification requirement is to estimate the Worst-Case Execution Time (WCET) of programs. These estimates are then used to predict the timing behavior of the overall system. The execution time of a program heavily depends on the underlying hardware, among which cache has the biggest influence. Analyzing cache behavior is very challenging due to the versatile cache features and complex execution environment. This article provides a survey on static cache analysis for real-time systems. We first present the challenges and static analysis techniques for independent programs with respect to different cache features. Then, the discussion is extended to cache analysis in complex execution environment, followed by a survey of existing tools based on static techniques for cache analysis. An outlook for future research is provided at last.
Cite as
Mingsong Lv, Nan Guan, Jan Reineke, Reinhard Wilhelm, and Wang Yi. A Survey on Static Cache Analysis for Real-Time Systems. In LITES, Volume 3, Issue 1 (2016). Leibniz Transactions on Embedded Systems, Volume 3, Issue 1, pp. 05:1-05:48, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2016)
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@Article{lv_et_al:LITES-v003-i001-a005,
author = {Lv, Mingsong and Guan, Nan and Reineke, Jan and Wilhelm, Reinhard and Yi, Wang},
title = {{A Survey on Static Cache Analysis for Real-Time Systems}},
journal = {Leibniz Transactions on Embedded Systems},
pages = {05:1--05:48},
ISSN = {2199-2002},
year = {2016},
volume = {3},
number = {1},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/LITES-v003-i001-a005},
doi = {10.4230/LITES-v003-i001-a005},
annote = {Keywords: Hard real-time, Cache analysis, Worst-case execution time}
}