Volume
OASIcs, Volume 108
Fourth Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2023)
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Series:
Open Access Series in Informatics (OASIcs)
Conference: Workshop on Next Generation Real-Time Embedded Systems (NG-RES)
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Editors
Publication Details
- published at: 2023-03-16
- Publisher: Schloss Dagstuhl – Leibniz-Zentrum für Informatik
- ISBN: 978-3-95977-268-6
- DBLP: db/conf/hipeac/ngres2023
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Document
Complete Volume
OASIcs, Volume 108, NG-RES 2023, Complete Volume
Abstract
OASIcs, Volume 108, NG-RES 2023, Complete Volume
Cite as
Fourth Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2023). Open Access Series in Informatics (OASIcs), Volume 108, pp. 1-98, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2023)
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@Proceedings{terraneo_et_al:OASIcs.NG-RES.2023,
title = {{OASIcs, Volume 108, NG-RES 2023, Complete Volume}},
booktitle = {Fourth Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2023)},
pages = {1--98},
series = {Open Access Series in Informatics (OASIcs)},
ISBN = {978-3-95977-268-6},
ISSN = {2190-6807},
year = {2023},
volume = {108},
editor = {Terraneo, Federico and Cattaneo, Daniele},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.NG-RES.2023},
URN = {urn:nbn:de:0030-drops-177300},
doi = {10.4230/OASIcs.NG-RES.2023},
annote = {Keywords: OASIcs, Volume 108, NG-RES 2023, Complete Volume}
}
Document
Front Matter
Front Matter, Table of Contents, Preface, Conference Organization
Abstract
Front Matter, Table of Contents, Preface, Conference Organization
Cite as
Fourth Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2023). Open Access Series in Informatics (OASIcs), Volume 108, pp. 0:i-0:x, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2023)
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@InProceedings{terraneo_et_al:OASIcs.NG-RES.2023.0,
author = {Terraneo, Federico and Cattaneo, Daniele},
title = {{Front Matter, Table of Contents, Preface, Conference Organization}},
booktitle = {Fourth Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2023)},
pages = {0:i--0:x},
series = {Open Access Series in Informatics (OASIcs)},
ISBN = {978-3-95977-268-6},
ISSN = {2190-6807},
year = {2023},
volume = {108},
editor = {Terraneo, Federico and Cattaneo, Daniele},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.NG-RES.2023.0},
URN = {urn:nbn:de:0030-drops-177312},
doi = {10.4230/OASIcs.NG-RES.2023.0},
annote = {Keywords: Front Matter, Table of Contents, Preface, Conference Organization}
}
Document
Invited Talk
Control Systems in the Presence of Computational Problems (Invited Talk)
Abstract
Feedback control is a central enabling technology in a wide range of applications. Control systems are at the core of energy distribution infrastructure, regulate the behaviour of engines in vehicles, and are embedded in household appliances like washing machines. Control is centred around the feedback mechanism. Sensors provide information about the current state of the physical environment. This is used to compute suitable control actions to fulfil performance requirements, that are then implemented by actuators. For example, adaptive cruise control systems use measurements from a range of sensors to determine how to adjust the throttle to automatically regulate the vehicle’s speed, while maintaining a safe distance from vehicles ahead.
Control actions are often calculated using hardware and software. Hence, the computation of the new control signals is subject to accidental faults, systematic issues, and software bugs. In practice, these computational problems are often ignored. But when can this be done safely? This talk will introduce a framework for analyzing the behaviour of control software subject to computational problems. The focus will be on the development of tools that can certify when control software is able to fulfil the system requirements, despite the presence of computational problems.
Cite as
Martina Maggio. Control Systems in the Presence of Computational Problems (Invited Talk). In Fourth Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2023). Open Access Series in Informatics (OASIcs), Volume 108, p. 1:1, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2023)
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@InProceedings{maggio:OASIcs.NG-RES.2023.1,
author = {Maggio, Martina},
title = {{Control Systems in the Presence of Computational Problems}},
booktitle = {Fourth Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2023)},
pages = {1:1--1:1},
series = {Open Access Series in Informatics (OASIcs)},
ISBN = {978-3-95977-268-6},
ISSN = {2190-6807},
year = {2023},
volume = {108},
editor = {Terraneo, Federico and Cattaneo, Daniele},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.NG-RES.2023.1},
URN = {urn:nbn:de:0030-drops-177320},
doi = {10.4230/OASIcs.NG-RES.2023.1},
annote = {Keywords: control systems, fault tolerance}
}
Document
IRQ Coloring: Mitigating Interrupt-Generated Interference on ARM Multicore Platforms
Abstract
Mixed-criticality systems, which consolidate workloads with different criticalities, must comply with stringent spatial and temporal isolation requirements imposed by safety-critical standards (e.g., ISO26262). This, per se, has proven to be a challenge with the advent of multicore platforms due to the inner interference created by multiple subsystems while disputing access to shared resources. With this work, we pioneer the concept of Interrupt (IRQ) coloring as a novel mechanism to minimize the interference created by co-existing interrupt-driven workloads. The main idea consists of selectively deactivating specific ("colored") interrupts if the QoS of critical workloads (e.g., Virtual Machines) drops below a well-defined threshold. The IRQ Coloring approach encompasses two artifacts, i.e., the IRQ Coloring Design-Time Tool (IRQ DTT) and the IRQ Coloring Run-Time Mechanism (IRQ RTM). In this paper, we focus on presenting the conceptual IRQ coloring design, describing the first prototype of the IRQ RTM on Bao hypervisor, and providing initial evidence about the effectiveness of the proposed approach on a synthetic use case.
Cite as
Diogo Costa, Luca Cuomo, Daniel Oliveira, Ida Maria Savino, Bruno Morelli, José Martins, Fabrizio Tronci, Alessandro Biasci, and Sandro Pinto. IRQ Coloring: Mitigating Interrupt-Generated Interference on ARM Multicore Platforms. In Fourth Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2023). Open Access Series in Informatics (OASIcs), Volume 108, pp. 2:1-2:13, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2023)
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@InProceedings{costa_et_al:OASIcs.NG-RES.2023.2,
author = {Costa, Diogo and Cuomo, Luca and Oliveira, Daniel and Savino, Ida Maria and Morelli, Bruno and Martins, Jos\'{e} and Tronci, Fabrizio and Biasci, Alessandro and Pinto, Sandro},
title = {{IRQ Coloring: Mitigating Interrupt-Generated Interference on ARM Multicore Platforms}},
booktitle = {Fourth Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2023)},
pages = {2:1--2:13},
series = {Open Access Series in Informatics (OASIcs)},
ISBN = {978-3-95977-268-6},
ISSN = {2190-6807},
year = {2023},
volume = {108},
editor = {Terraneo, Federico and Cattaneo, Daniele},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.NG-RES.2023.2},
URN = {urn:nbn:de:0030-drops-177333},
doi = {10.4230/OASIcs.NG-RES.2023.2},
annote = {Keywords: IRQ coloring, Interrupt Interference, Mixed-Criticality Systems, Hypervisors, Bao, Arm}
}
Document
Beyond the Threaded Programming Model on Real-Time Operating Systems
Abstract
The use of a real-time operating system (RTOS) raises the abstraction level for embedded systems design when compared to traditional bare-metal programming, resulting in simpler and more reusable application code. Modern RTOSes for resource-constrained platforms, like Zephyr and FreeRTOS, also offer threading support, but this kind of shared memory concurrency is a poor fit for expressing the reactive and interactive behaviors that are common in embedded systems. To address this, alternative concurrency models like the actor model or communicating sequential processes have been proposed. While those alternatives enable reactive design patterns, they fail to deliver determinism and do not address timing. This makes it difficult to verify that implemented behavior is as intended and impossible to specify timing constraints in a portable way. This makes it hard to create reusable library components out of common embedded design patterns, forcing developers to keep reinventing the wheel for each application and each platform. In this paper, we introduce the embedded target of Lingua Franca (LF) as a means to move beyond the threaded programming model provided by RTOSes and improve the state of the art in embedded programming. LF is based on the reactor model of computation, which is reactive, deterministic, and timed, providing a means to express concurrency and timing in a platform-independent way. We compare the performance of LF versus threaded C code - both running on Zephyr - in terms of response time, timing precision, throughput, and memory footprint.
Cite as
Erling Rennemo Jellum, Shaokai Lin, Peter Donovan, Efsane Soyer, Fuzail Shakir, Torleiv Bryne, Milica Orlandic, Marten Lohstroh, and Edward A. Lee. Beyond the Threaded Programming Model on Real-Time Operating Systems. In Fourth Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2023). Open Access Series in Informatics (OASIcs), Volume 108, pp. 3:1-3:13, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2023)
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@InProceedings{jellum_et_al:OASIcs.NG-RES.2023.3,
author = {Jellum, Erling Rennemo and Lin, Shaokai and Donovan, Peter and Soyer, Efsane and Shakir, Fuzail and Bryne, Torleiv and Orlandic, Milica and Lohstroh, Marten and Lee, Edward A.},
title = {{Beyond the Threaded Programming Model on Real-Time Operating Systems}},
booktitle = {Fourth Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2023)},
pages = {3:1--3:13},
series = {Open Access Series in Informatics (OASIcs)},
ISBN = {978-3-95977-268-6},
ISSN = {2190-6807},
year = {2023},
volume = {108},
editor = {Terraneo, Federico and Cattaneo, Daniele},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.NG-RES.2023.3},
URN = {urn:nbn:de:0030-drops-177348},
doi = {10.4230/OASIcs.NG-RES.2023.3},
annote = {Keywords: Real time, concurrency, reactors, Lingua Franca, RTOS}
}
Document
Efficient Abstraction of Clock Synchronization at the Operating System Level
Abstract
Distributed embedded systems are emerging and gaining importance in various domains, including industrial control applications where time determinism - hence network clock synchronization - is fundamental. In modern applications, moreover, this core functionality is required by many different software components, from OS kernel and radio stack up to applications. An abstraction layer devoted to handling time needs therefore introducing, and to encapsulate time corrections at the lowest possible level, the said layer should take the form of a timer device driver offering a Virtual Clock to the entire system. In this paper we show that doing so introduces a nonlinearity in the dynamics of the clock, and we design a controller based on feedback linearization to handle the issue. To put the idea to work, we extend the Miosix RTOS with a generic interface allowing to implement virtual clocks, including the newly designed controller that we call FLOPSYNC-3 after its ancestor. Also, we introduce the resulting virtual clock in the TDMH [Terraneo et al., 2018] real-time wireless mesh protocol.
Cite as
Alessandro Sorrentino, Federico Terraneo, and Alberto Leva. Efficient Abstraction of Clock Synchronization at the Operating System Level. In Fourth Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2023). Open Access Series in Informatics (OASIcs), Volume 108, pp. 4:1-4:11, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2023)
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@InProceedings{sorrentino_et_al:OASIcs.NG-RES.2023.4,
author = {Sorrentino, Alessandro and Terraneo, Federico and Leva, Alberto},
title = {{Efficient Abstraction of Clock Synchronization at the Operating System Level}},
booktitle = {Fourth Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2023)},
pages = {4:1--4:11},
series = {Open Access Series in Informatics (OASIcs)},
ISBN = {978-3-95977-268-6},
ISSN = {2190-6807},
year = {2023},
volume = {108},
editor = {Terraneo, Federico and Cattaneo, Daniele},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.NG-RES.2023.4},
URN = {urn:nbn:de:0030-drops-177357},
doi = {10.4230/OASIcs.NG-RES.2023.4},
annote = {Keywords: Clock synchronization, Real-time operating systems, Embedded software, Real-time control}
}
Document
Response Time Analysis for RT-MQTT Protocol Grounded on SDN
Abstract
The current industry trend is to replace the use of custom components with standards-based Commercially available Off-The-Shelf (COTS) based hardware and protocols. Furthermore, the emergence of new industrial paradigms, such as Industry 4.0 and the Industrial Internet of Things, sets additional requirements regarding e.g. scale, transparency, agility, flexibility and efficiency. Therefore, in these domains, application layer protocols such as Message Queuing Telemetry Transport protocol (MQTT) are gaining popularity, in result of their simplicity, scalability, low resource-usage and decoupling between end nodes. However, such protocols were not designed for real-time applications, missing key features such as determinism and latency bounds. A recent work proposed extending MQTT with real-time services, taking advantage of Software Defined Networking (SDN) to manage the network resource. These extensions allow applications to specify real-time requirements that are then captured by a resource manager and used to reserve the necessary resources at the network layer. This paper shows that such MQTT extended architecture is analyzable from a worst-case timing perspective. We derive a system model that captures the real-time features and we present a response-time analysis to assess the schedulability of the real-time traffic. Finally, we validate the analysis with a set of experimental results.
Cite as
Ehsan Shahri, Paulo Pedreiras, and Luis Almeida. Response Time Analysis for RT-MQTT Protocol Grounded on SDN. In Fourth Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2023). Open Access Series in Informatics (OASIcs), Volume 108, pp. 5:1-5:15, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2023)
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@InProceedings{shahri_et_al:OASIcs.NG-RES.2023.5,
author = {Shahri, Ehsan and Pedreiras, Paulo and Almeida, Luis},
title = {{Response Time Analysis for RT-MQTT Protocol Grounded on SDN}},
booktitle = {Fourth Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2023)},
pages = {5:1--5:15},
series = {Open Access Series in Informatics (OASIcs)},
ISBN = {978-3-95977-268-6},
ISSN = {2190-6807},
year = {2023},
volume = {108},
editor = {Terraneo, Federico and Cattaneo, Daniele},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.NG-RES.2023.5},
URN = {urn:nbn:de:0030-drops-177364},
doi = {10.4230/OASIcs.NG-RES.2023.5},
annote = {Keywords: Real-time systems, OpenFlow, fixed-priority non-preemptive scheduling, response time analysis, MQTT}
}
Document
Throughput and Memory Optimization for Parallel Implementations of Dataflow Networks Using Multi-Reader Buffers
Abstract
In this paper, we introduce the concept of Multi-Reader Buffers (MRBs) for high throughput and memory-efficient implementation of dataflow applications. Our work is motivated by the huge amount of data that needs to be processed and typically accessed in a FIFO manner, particularly in image and video processing applications. Here, multi-cast, fork, and merge operator implementations known today produce huge memory overheads by storing and communicating copies of the same data. As a remedy, we first introduce MRBs as buffers preserving FIFO semantics for a finite number of readers of the same data while storing each data item only once. Second, we present an approach for memory minimization of data flow networks by replacing all multi-cast actors and connected FIFOs with MRBs. Third, we present a Design Space Exploration approach to selectively replace multi-cast actors with MRBs in order to explore memory, throughput, and processor resource allocation tradeoffs. Our results show that the explored Pareto fronts of our approach improve the solution quality over a reference by 78% in average for six benchmark applications in terms of a hypervolume indicator.
Cite as
Martin Letras, Joachim Falk, and Jürgen Teich. Throughput and Memory Optimization for Parallel Implementations of Dataflow Networks Using Multi-Reader Buffers. In Fourth Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2023). Open Access Series in Informatics (OASIcs), Volume 108, pp. 6:1-6:13, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2023)
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@InProceedings{letras_et_al:OASIcs.NG-RES.2023.6,
author = {Letras, Martin and Falk, Joachim and Teich, J\"{u}rgen},
title = {{Throughput and Memory Optimization for Parallel Implementations of Dataflow Networks Using Multi-Reader Buffers}},
booktitle = {Fourth Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2023)},
pages = {6:1--6:13},
series = {Open Access Series in Informatics (OASIcs)},
ISBN = {978-3-95977-268-6},
ISSN = {2190-6807},
year = {2023},
volume = {108},
editor = {Terraneo, Federico and Cattaneo, Daniele},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.NG-RES.2023.6},
URN = {urn:nbn:de:0030-drops-177374},
doi = {10.4230/OASIcs.NG-RES.2023.6},
annote = {Keywords: Dataflow, Memory Optimization, MPSoCs, Design Space Exploration}
}
Document
RAVEN: Reinforcement Learning for Generating Verifiable Run-Time Requirement Enforcers for MPSoCs
Abstract
In embedded systems, applications frequently have to meet non-functional requirements regarding, e.g., real-time or energy consumption constraints, when executing on a given MPSoC target platform.
Feedback-based controllers have been proposed that react to transient environmental factors by adapting the DVFS settings or degree of parallelism following some predefined control strategy. However, it is, in general, not possible to give formal guarantees for the obtained controllers to satisfy a given set of non-functional requirements. Run-time requirement enforcement has emerged as a field of research for the enforcement of non-functional requirements at run-time, allowing to define and formally verify properties on respective control strategies specified by automata. However, techniques for the automatic generation of such controllers have not yet been established.
In this paper, we propose a technique using reinforcement learning to automatically generate verifiable feedback-based enforcers. For that, we train a control policy based on a representative input sequence at design time. The learned control strategy is then transformed into a verifiable enforcement automaton which constitutes our run-time control model that can handle unseen input data. As a case study, we apply the approach to generate controllers that are able to increase the probability of satisfying a given set of requirement verification goals compared to multiple state-of-the-art approaches, as can be verified by model checkers.
Cite as
Khalil Esper, Jan Spieck, Pierre-Louis Sixdenier, Stefan Wildermann, and Jürgen Teich. RAVEN: Reinforcement Learning for Generating Verifiable Run-Time Requirement Enforcers for MPSoCs. In Fourth Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2023). Open Access Series in Informatics (OASIcs), Volume 108, pp. 7:1-7:16, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2023)
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@InProceedings{esper_et_al:OASIcs.NG-RES.2023.7,
author = {Esper, Khalil and Spieck, Jan and Sixdenier, Pierre-Louis and Wildermann, Stefan and Teich, J\"{u}rgen},
title = {{RAVEN: Reinforcement Learning for Generating Verifiable Run-Time Requirement Enforcers for MPSoCs}},
booktitle = {Fourth Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2023)},
pages = {7:1--7:16},
series = {Open Access Series in Informatics (OASIcs)},
ISBN = {978-3-95977-268-6},
ISSN = {2190-6807},
year = {2023},
volume = {108},
editor = {Terraneo, Federico and Cattaneo, Daniele},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.NG-RES.2023.7},
URN = {urn:nbn:de:0030-drops-177380},
doi = {10.4230/OASIcs.NG-RES.2023.7},
annote = {Keywords: Verification, Runtime Requirement Enforcement, Reinforcement Learning}
}