Volume
OASIcs, Volume 140
7th Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2026)
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Open Access Series in Informatics (OASIcs)
Conference: Workshop on Next Generation Real-Time Embedded Systems (NG-RES)
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Publication Details
- published at: 2026-03-10
- Publisher: Schloss Dagstuhl – Leibniz-Zentrum für Informatik
- ISBN: 978-3-95977-415-4
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Document
Complete Volume
OASIcs, Volume 140, NG-RES 2026, Complete Volume
Abstract
OASIcs, Volume 140, NG-RES 2026, Complete Volume
Cite as
7th Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2026). Open Access Series in Informatics (OASIcs), Volume 140, pp. 1-76, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2026)
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@Proceedings{ali_et_al:OASIcs.NG-RES.2026,
title = {{OASIcs, Volume 140, NG-RES 2026, Complete Volume}},
booktitle = {7th Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2026)},
pages = {1--76},
series = {Open Access Series in Informatics (OASIcs)},
ISBN = {978-3-95977-415-4},
ISSN = {2190-6807},
year = {2026},
volume = {140},
editor = {Ali, Hazem Ismail and Kurunathan, Harrison},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.NG-RES.2026},
URN = {urn:nbn:de:0030-drops-256593},
doi = {10.4230/OASIcs.NG-RES.2026},
annote = {Keywords: OASIcs, Volume 140, NG-RES 2026, Complete Volume}
}
Document
Front Matter
Front Matter, Table of Contents, Preface, Conference Organization
Abstract
Front Matter, Table of Contents, Preface, Conference Organization
Cite as
7th Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2026). Open Access Series in Informatics (OASIcs), Volume 140, pp. 0:i-0:x, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2026)
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@InProceedings{ali_et_al:OASIcs.NG-RES.2026.0,
author = {Ali, Hazem Ismail and Kurunathan, Harrison},
title = {{Front Matter, Table of Contents, Preface, Conference Organization}},
booktitle = {7th Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2026)},
pages = {0:i--0:x},
series = {Open Access Series in Informatics (OASIcs)},
ISBN = {978-3-95977-415-4},
ISSN = {2190-6807},
year = {2026},
volume = {140},
editor = {Ali, Hazem Ismail and Kurunathan, Harrison},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.NG-RES.2026.0},
URN = {urn:nbn:de:0030-drops-256580},
doi = {10.4230/OASIcs.NG-RES.2026.0},
annote = {Keywords: Front Matter, Table of Contents, Preface, Conference Organization}
}
Document
Computer Vision Integration for Automated Piece Positioning in an Industry 4.0 Setup
Abstract
This paper presents the design and development of an alternative, cost-effective automated piece positioning system, specifically tailored for Small and Medium-sized Enterprises (SMEs), which integrates computer vision with EtherCAT-controlled servo motors. The proposed method combines a robust vision system with an AI-enhanced algorithm based on edge detection to precisely identify object contours. This enables a Programmable Logic Controller (PLC) to control the servo motor, adjusting the piece’s angle with high accuracy. Experimental results demonstrate the solution’s practical viability, achieving a minimal angular oscillation of less than 0.0012° and a promising low image processing time of approximately 20ms, showcasing its potential for enhancing manufacturing efficiency and quality in industrial applications.
Cite as
Augusto de Souza, Alexandre dos Santos Roque, Carlos Eduardo Pereira, and Edison Pignaton de Freitas. Computer Vision Integration for Automated Piece Positioning in an Industry 4.0 Setup. In 7th Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2026). Open Access Series in Informatics (OASIcs), Volume 140, pp. 1:1-1:11, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2026)
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@InProceedings{desouza_et_al:OASIcs.NG-RES.2026.1,
author = {de Souza, Augusto and dos Santos Roque, Alexandre and Pereira, Carlos Eduardo and de Freitas, Edison Pignaton},
title = {{Computer Vision Integration for Automated Piece Positioning in an Industry 4.0 Setup}},
booktitle = {7th Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2026)},
pages = {1:1--1:11},
series = {Open Access Series in Informatics (OASIcs)},
ISBN = {978-3-95977-415-4},
ISSN = {2190-6807},
year = {2026},
volume = {140},
editor = {Ali, Hazem Ismail and Kurunathan, Harrison},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.NG-RES.2026.1},
URN = {urn:nbn:de:0030-drops-254191},
doi = {10.4230/OASIcs.NG-RES.2026.1},
annote = {Keywords: Industry 4.0, Automation, Vision systems, Piece positioning, Servo motors}
}
Document
Schedulability Analysis of OpenMP Applications Under Heuristic Task-To-Thread Mapping
Abstract
Task-to-thread mapping is a key process in parallel applications to achieve the best possible performance. This process is even more challenging when it is required to meet the schedulability and timing requirements of critical systems. In these systems, mapping tasks to threads is usually carried out using static scheduling (i.e., offline mapping) to improve system schedulability, with several approaches being presented in the literature. Nevertheless, there has been little analysis on the impact that these static mapping approaches have on the schedulability of applications exploiting OpenMP, a model increasingly seen as a suitable mechanism to leverage the potential of parallel and heterogeneous processor architectures. This paper, therefore, performs a throughout evaluation of the recently presented heuristic task-to-thread mapping working with different heuristics through allocation and dispatching phases, compared with state-of-the-art, in terms of schedulability. This process is performed using a state-of-the-art schedulability analysis methodology through an integration of our simulator and an existing schedulability toolset. This evaluation allows for identifying the static heuristic mapping approaches that achieve tighter schedulability analysis than other methods in the literature.
Cite as
Mohammad Samadi, Tiago Carvalho, Luís Miguel Pinho, and Sara Royuela. Schedulability Analysis of OpenMP Applications Under Heuristic Task-To-Thread Mapping. In 7th Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2026). Open Access Series in Informatics (OASIcs), Volume 140, pp. 2:1-2:12, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2026)
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@InProceedings{samadi_et_al:OASIcs.NG-RES.2026.2,
author = {Samadi, Mohammad and Carvalho, Tiago and Pinho, Lu{\'\i}s Miguel and Royuela, Sara},
title = {{Schedulability Analysis of OpenMP Applications Under Heuristic Task-To-Thread Mapping}},
booktitle = {7th Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2026)},
pages = {2:1--2:12},
series = {Open Access Series in Informatics (OASIcs)},
ISBN = {978-3-95977-415-4},
ISSN = {2190-6807},
year = {2026},
volume = {140},
editor = {Ali, Hazem Ismail and Kurunathan, Harrison},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.NG-RES.2026.2},
URN = {urn:nbn:de:0030-drops-254204},
doi = {10.4230/OASIcs.NG-RES.2026.2},
annote = {Keywords: OpenMP, task-to-thread mapping, heuristics, response time, schedulability}
}
Document
Integrated Memory Grouping and Power-Aware MBIST Scheduling for MPSoCs
Abstract
Memory Built-In Self-Test (MBIST) is a widely adopted technique for testing memory. In modern large-scale SoCs, hundreds to thousands of embedded memories are integrated, and to test them efficiently, methods that group memories and test them in parallel within each group are employed. However, many existing approaches either do not account for test scheduling or rely on evolutionary methods, such as genetic algorithms (GAs), for grouping, which incur high computational costs. In this work, we propose a framework that covers the flow from memory grouping to test scheduling. Taking the specifications and layout information of multiple SRAMs into account, the framework comprises a flexible, fast memory grouping method and a scheduling method that minimizes the total test time under a power-constrained constraint. In the proposed approach, DBSCAN and rectangular partitioning are used to perform fast grouping while suppressing long routing connections, and an LPT-based greedy heuristic is employed to shorten the total test time under constraints on the power limit and the number of simultaneously active BIST controllers. Experimental evaluation using SRAM placement data based on the ASAP7 PDK shows that, compared with existing K-means, Greedy, and GA-based methods, the proposed method reduces the number of groups by up to 48% while achieving approximately 87× speedup in clustering runtime. Furthermore, compared with a commercial Industrial Solution, it reduces the test time by 53%. These results demonstrate that the proposed method provides high scalability and practical effectiveness for MBIST design, even in large-scale MPSoCs with a large number and variety of embedded memories.
Cite as
Koki Asahina and Yasuhiko Nakashima. Integrated Memory Grouping and Power-Aware MBIST Scheduling for MPSoCs. In 7th Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2026). Open Access Series in Informatics (OASIcs), Volume 140, pp. 3:1-3:13, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2026)
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@InProceedings{asahina_et_al:OASIcs.NG-RES.2026.3,
author = {Asahina, Koki and Nakashima, Yasuhiko},
title = {{Integrated Memory Grouping and Power-Aware MBIST Scheduling for MPSoCs}},
booktitle = {7th Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2026)},
pages = {3:1--3:13},
series = {Open Access Series in Informatics (OASIcs)},
ISBN = {978-3-95977-415-4},
ISSN = {2190-6807},
year = {2026},
volume = {140},
editor = {Ali, Hazem Ismail and Kurunathan, Harrison},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.NG-RES.2026.3},
URN = {urn:nbn:de:0030-drops-254214},
doi = {10.4230/OASIcs.NG-RES.2026.3},
annote = {Keywords: MBIST, DfT, Memory Grouping, Power-Aware Scheduling}
}
Document
Efficient Design of High-Resolution Timekeeping in Real-Time Operating Systems
Abstract
High-resolution timekeeping is a desirable feature in real-time operating systems targeting microcontrollers, which traditionally has been held back due to its impact on context switch overhead. In this paper we present the design of a timing subsystem that decouples preemption from the timekeeping operation. This design, making use of 1+N hardware timers, significantly speeds up the context switch code while scaling effectively to multi-core microcontroller architectures with N cores. Preliminary experimental results on the Miosix fluid kernel show the effectiveness of the proposed design.
Cite as
Federico Terraneo and Daniele Cattaneo. Efficient Design of High-Resolution Timekeeping in Real-Time Operating Systems. In 7th Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2026). Open Access Series in Informatics (OASIcs), Volume 140, pp. 4:1-4:15, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2026)
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@InProceedings{terraneo_et_al:OASIcs.NG-RES.2026.4,
author = {Terraneo, Federico and Cattaneo, Daniele},
title = {{Efficient Design of High-Resolution Timekeeping in Real-Time Operating Systems}},
booktitle = {7th Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2026)},
pages = {4:1--4:15},
series = {Open Access Series in Informatics (OASIcs)},
ISBN = {978-3-95977-415-4},
ISSN = {2190-6807},
year = {2026},
volume = {140},
editor = {Ali, Hazem Ismail and Kurunathan, Harrison},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.NG-RES.2026.4},
URN = {urn:nbn:de:0030-drops-254228},
doi = {10.4230/OASIcs.NG-RES.2026.4},
annote = {Keywords: RTOS, Task Scheduling, Multiprocessing}
}
Document
SEKHMET: Hash-Chained Perception Contracts for Heterogeneous Real-Time Edge Clusters
Abstract
Real-time perception pipelines on edge clusters are often scheduled as ordinary latency-sensitive pods, even when safety depends on sustained throughput and stable model outputs. This paper presents SEKHMET (Scheduling Edge Kubernetes with Hash-chained Monitoring of End-to-end Telemetry), a perception-aware orchestration layer for lightweight Kubernetes (K3s) clusters that exports window-level perception status as a control-plane signal. SEKHMET evaluates a perception-integrity contract (PIC) once per fixed-duration window and commits each window outcome into a hash-chained perception root that is published to an otherwise unmodified K3s control plane. The prototype uses a Raspberry Pi 5 perception-root node with a Hailo-8L accelerator, USB camera, and GPS receiver running a YOLOv8s detector, while up to five additional nodes generate elastic interference via swarm-stress. Under contract-unaware scheduling with multi-node interference, the end-to-end perception loop delivers ∼0.8-2.2 FPS and violates the PIC timing requirement in most of 214 windows, despite apparently healthy CPU and memory metrics. Under the same and heavier interference, SEKHMET sustains 27-30 FPS with contract_ok = True across 400 protected windows while publishing one 96-byte record per T=5s window (19.2 B/s control-plane payload). These results show that making perception requirements control-plane-visible can turn fragile best-effort perception into a protected cluster-level resource on commodity edge hardware.
Cite as
Mohamed El-Hadedy. SEKHMET: Hash-Chained Perception Contracts for Heterogeneous Real-Time Edge Clusters. In 7th Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2026). Open Access Series in Informatics (OASIcs), Volume 140, pp. 5:1-5:12, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2026)
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@InProceedings{elhadedy:OASIcs.NG-RES.2026.5,
author = {El-Hadedy, Mohamed},
title = {{SEKHMET: Hash-Chained Perception Contracts for Heterogeneous Real-Time Edge Clusters}},
booktitle = {7th Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2026)},
pages = {5:1--5:12},
series = {Open Access Series in Informatics (OASIcs)},
ISBN = {978-3-95977-415-4},
ISSN = {2190-6807},
year = {2026},
volume = {140},
editor = {Ali, Hazem Ismail and Kurunathan, Harrison},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.NG-RES.2026.5},
URN = {urn:nbn:de:0030-drops-254239},
doi = {10.4230/OASIcs.NG-RES.2026.5},
annote = {Keywords: edge clusters, K3s, Kubernetes, real-time perception, scheduling, integrity contracts, hash chaining, Hailo-8L}
}