DARTS, Volume 10, Issue 1

Special Issue of the 36th Euromicro Conference on Real-Time Systems (ECRTS 2024)



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Publication Details

  • published at: 2024-07-04
  • Publisher: Schloss Dagstuhl – Leibniz-Zentrum für Informatik
  • ISBN: 978-3-95977-327-0
  • DBLP: db/journals/darts/darts10

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Document
Front Matter
Front Matter, Table of Contents, Artifact Evaluation Process, Artifact Evaluation Committee

Authors: Matthias Becker and Catherine E. Nemitz


Abstract
Front Matter, Table of Contents, Artifact Evaluation Process, Artifact Evaluation Committee

Cite as

Special Issue of the 36th Euromicro Conference on Real-Time Systems (ECRTS 2024). Dagstuhl Artifacts Series (DARTS), Volume 10, Issue 1, pp. 0:i-0:x, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2024)


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@Article{becker_et_al:DARTS.10.1.0,
  author =	{Becker, Matthias and Nemitz, Catherine E.},
  title =	{{Front Matter, Table of Contents, Artifact Evaluation Process, Artifact Evaluation Committee}},
  pages =	{0:i--0:x},
  journal =	{Dagstuhl Artifacts Series},
  ISBN =	{978-3-95977-327-0},
  ISSN =	{2509-8195},
  year =	{2024},
  volume =	{10},
  number =	{1},
  editor =	{Becker, Matthias and Nemitz, Catherine E.},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/DARTS.10.1.0},
  URN =		{urn:nbn:de:0030-drops-203223},
  doi =		{10.4230/DARTS.10.1.0},
  annote =	{Keywords: Front Matter, Table of Contents, Artifact Evaluation Process, Artifact Evaluation Committee}
}
Document
Artifact
Predictable GPU Sharing in Component-Based Real-Time Systems (Artifact)

Authors: Syed W. Ali, Zelin Tong, Joseph Goh, and James H. Anderson


Abstract
This paper presents a real-time locking protocol whose design was motivated by the goal of enabling safe GPU sharing in time-sliced component-based systems. This locking protocol enables a GPU to be shared concurrently across, and utilized within, isolated components with predictable execution times. It relies on a novel resizing technique where GPU work is dimensioned on-the-fly to run on partitions of an NVIDIA GPU. This technique can be applied to any component that internally utilizes global CPU scheduling. The proposed locking protocol enables increased GPU parallelism and reduces GPU capacity loss with analytically provable benefits.

Cite as

Syed W. Ali, Zelin Tong, Joseph Goh, and James H. Anderson. Predictable GPU Sharing in Component-Based Real-Time Systems (Artifact). In Special Issue of the 36th Euromicro Conference on Real-Time Systems (ECRTS 2024). Dagstuhl Artifacts Series (DARTS), Volume 10, Issue 1, pp. 1:1-1:5, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2024)


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@Article{ali_et_al:DARTS.10.1.1,
  author =	{Ali, Syed W. and Tong, Zelin and Goh, Joseph and Anderson, James H.},
  title =	{{Predictable GPU Sharing in Component-Based Real-Time Systems (Artifact)}},
  pages =	{1:1--1:5},
  journal =	{Dagstuhl Artifacts Series},
  ISBN =	{978-3-95977-327-0},
  ISSN =	{2509-8195},
  year =	{2024},
  volume =	{10},
  number =	{1},
  editor =	{Ali, Syed W. and Tong, Zelin and Goh, Joseph and Anderson, James H.},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/DARTS.10.1.1},
  URN =		{urn:nbn:de:0030-drops-203236},
  doi =		{10.4230/DARTS.10.1.1},
  annote =	{Keywords: GPU locking protocols, real-time locking protocols, priority-inversion blocking, component-based systems}
}
Document
Artifact
Crêpe: Clock Reconfigurability for Preemption Control (Artifact)

Authors: Eva Dengler and Peter Wägemann


Abstract
With the emergence of embedded system-on-chip (SoC) platforms, the development of energy-constrained real-time systems brings numerous novel challenges for optimal resource consumption. On these modern hardware platforms, complex clock subsystems make it possible to tradeoff between temporal performance and energy efficiency by reconfiguring the system, which exceeds the state-of-the-art of existing dynamic-voltage-frequency-scaling (DVFS) scheduling schemes. On embedded real-time systems, the usage of the devices (e.g., transceiver/memory/sensor devices) is an essential component to be able to interact with the surrounding world. Each device has precedence constraints with respect to specific clock sources and their settings. Therefore, to select resource-optimal configurations, we need to adapt the clock subsystem, which becomes especially challenging in the presence of asynchronous preemptions, often found during device interaction. This artifact evaluation covers the work of Crêpe, an approach to clock-reconfiguration-aware preemption control on systems with devices. Crêpe makes use of the target platform’s clock subsystem, possible idle modes, and the reconfiguration penalties for adapting the clock subsystem. By combining a hardware model for the device under investigation with an awareness of the required clock configuration for each task, as well as possible interrupts causing preemptions during runtime, Crêpe employs a mathematical formalization to determine energy-minimal configuration sequences while meeting all given deadlines. Before runtime, Crêpe solves the mathematical problem with standard mathematical solver tools and generates optimal execution strategies and clock-system reconfigurations before runtime. These offline-generated schedules are then assessed by the dispatcher during runtime, leading to an overall minimized energy consumption with minimal overhead during execution. Crêpe also consists of an implementation based on a widely-used SoC platform (i.e., ESP32-C3) and an automated testbed for comprehensive energy-consumption evaluations. This artifact evaluation makes use of these to validate Crêpe’s claim of selecting resource-optimal settings under worst-case considerations by reproducing our results shown in the related Crêpe paper [Eva Dengler and Peter Wägemann, 2024].

Cite as

Eva Dengler and Peter Wägemann. Crêpe: Clock Reconfigurability for Preemption Control (Artifact). In Special Issue of the 36th Euromicro Conference on Real-Time Systems (ECRTS 2024). Dagstuhl Artifacts Series (DARTS), Volume 10, Issue 1, pp. 2:1-2:3, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2024)


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@Article{dengler_et_al:DARTS.10.1.2,
  author =	{Dengler, Eva and W\"{a}gemann, Peter},
  title =	{{Cr\^{e}pe: Clock Reconfigurability for Preemption Control (Artifact)}},
  pages =	{2:1--2:3},
  journal =	{Dagstuhl Artifacts Series},
  ISBN =	{978-3-95977-327-0},
  ISSN =	{2509-8195},
  year =	{2024},
  volume =	{10},
  number =	{1},
  editor =	{Dengler, Eva and W\"{a}gemann, Peter},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/DARTS.10.1.2},
  URN =		{urn:nbn:de:0030-drops-203244},
  doi =		{10.4230/DARTS.10.1.2},
  annote =	{Keywords: energy-constrained real-time systems, time/energy tradeoff, system-on-chip, energy-aware real-time scheduling, resource minimization, preemption control, worst-case energy consumption (WCEC), worst-case execution-time (WCET), static whole-system analysis}
}
Document
Artifact
Autonomy Today: Many Delay-Prone Black Boxes (Artifact)

Authors: Sizhe Liu, Rohan Wagle, James H. Anderson, Ming Yang, Chi Zhang, and Yunhua Li


Abstract
Machine-learning (ML) technology has been a key enabler in the push towards realizing ever more sophisticated autonomous-driving features. In deploying such technology, the automotive industry has relied heavily on using "black-box" software and hardware components that were originally intended for non-safety-critical contexts, without a full understanding of their real-time capabilities. A prime example of such a component is CUDA, which is fundamental to the acceleration of ML algorithms using NVIDIA GPUs. In this paper, evidence is presented demonstrating that CUDA can cause unbounded task delays. Such delays are the result of CUDA’s usage of synchronization mechanisms in the POSIX thread (pthread) library, so the latter is implicated as a delay-prone component as well. Such synchronization delays are shown to be the source of a system failure that occurred in an actual autonomous vehicle system during testing at WeRide. Motivated by these findings, a broader experimental study is presented that demonstrates several real-time deficiencies in CUDA, the glibc pthread library, Linux, and the POSIX interface of the safety-certified QNX Operating System for Safety. Partial mitigations for these deficiencies are presented and further actions are proposed for real-time researchers and developers to integrate more complete mitigations.

Cite as

Sizhe Liu, Rohan Wagle, James H. Anderson, Ming Yang, Chi Zhang, and Yunhua Li. Autonomy Today: Many Delay-Prone Black Boxes (Artifact). In Special Issue of the 36th Euromicro Conference on Real-Time Systems (ECRTS 2024). Dagstuhl Artifacts Series (DARTS), Volume 10, Issue 1, pp. 3:1-3:3, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2024)


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@Article{liu_et_al:DARTS.10.1.3,
  author =	{Liu, Sizhe and Wagle, Rohan and Anderson, James H. and Yang, Ming and Zhang, Chi and Li, Yunhua},
  title =	{{Autonomy Today: Many Delay-Prone Black Boxes (Artifact)}},
  pages =	{3:1--3:3},
  journal =	{Dagstuhl Artifacts Series},
  ISBN =	{978-3-95977-327-0},
  ISSN =	{2509-8195},
  year =	{2024},
  volume =	{10},
  number =	{1},
  editor =	{Liu, Sizhe and Wagle, Rohan and Anderson, James H. and Yang, Ming and Zhang, Chi and Li, Yunhua},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/DARTS.10.1.3},
  URN =		{urn:nbn:de:0030-drops-203259},
  doi =		{10.4230/DARTS.10.1.3},
  annote =	{Keywords: autonomous driving, CUDA programming, locking protocols, POSIX thread, operating systems, machine learning systems, real-time systems}
}
Document
Artifact
The Omnivisor: A real-time static partitioning hypervisor extension for heterogeneous core virtualization over MPSoCs (Artifact)

Authors: Daniele Ottaviano, Francesco Ciraolo, Renato Mancuso, and Marcello Cinque


Abstract
Following the needs of industrial applications, virtualization has emerged as one of the most effective approaches for the consolidation of mixed-criticality systems while meeting tight constraints in terms of space, weight, power, and cost (SWaP-C). In embedded platforms with homogeneous processors, a wealth of works have proposed designs and techniques to enforce spatio-temporal isolation by leveraging well-understood virtualization support. Unfortunately, achieving the same goal on heterogeneous MultiProcessor Systems-on-Chip (MPSoCs) has been largely overlooked. Modern hypervisors are designed to operate exclusively on main cores, with little or no consideration given to other co-processors within the system, such as small microcontroller-level CPUs or soft-cores deployed on programmable logic (FPGA). Typically, hypervisors consider co-processors as I/O devices allocated to virtual machines that run on primary cores, yielding full control and responsibility over them. Nevertheless, inadequate management of these resources can lead to spatio-temporal isolation issues within the system. In this paper, we propose the Omnivisor model as a paradigm for the holistic management of heterogeneous platforms. The model generalizes the features of real-time static partitioning hypervisors to enable the execution of virtual machines on processors with different Instruction Set Architectures (ISAs) within the same MPSoC. Moreover, the Omnivisor ensures temporal and spatial isolation between virtual machines by integrating and leveraging a variety of hardware and software protection mechanisms. The presented approach not only expands the scope of virtualization in MPSoCs but also enhances the overall system reliability and real-time performance for mixed-criticality applications. A full open-source reference implementation of the Omnivisor based on the Jailhouse hypervisor is provided, targeting ARM real-time processing units and RISC-V soft-cores on FPGA. Experimental results on real hardware show the benefits of the solution, in terms of the seamless launch of virtual machines on different ISAs, and spatial/temporal isolation, enhanced with regulation policies.

Cite as

Daniele Ottaviano, Francesco Ciraolo, Renato Mancuso, and Marcello Cinque. The Omnivisor: A real-time static partitioning hypervisor extension for heterogeneous core virtualization over MPSoCs (Artifact). In Special Issue of the 36th Euromicro Conference on Real-Time Systems (ECRTS 2024). Dagstuhl Artifacts Series (DARTS), Volume 10, Issue 1, pp. 4:1-4:7, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2024)


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@Article{ottaviano_et_al:DARTS.10.1.4,
  author =	{Ottaviano, Daniele and Ciraolo, Francesco and Mancuso, Renato and Cinque, Marcello},
  title =	{{The Omnivisor: A real-time static partitioning hypervisor extension for heterogeneous core virtualization over MPSoCs (Artifact)}},
  pages =	{4:1--4:7},
  journal =	{Dagstuhl Artifacts Series},
  ISBN =	{978-3-95977-327-0},
  ISSN =	{2509-8195},
  year =	{2024},
  volume =	{10},
  number =	{1},
  editor =	{Ottaviano, Daniele and Ciraolo, Francesco and Mancuso, Renato and Cinque, Marcello},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/DARTS.10.1.4},
  URN =		{urn:nbn:de:0030-drops-203267},
  doi =		{10.4230/DARTS.10.1.4},
  annote =	{Keywords: Mixed-Criticality, Embedded Virtualization, Real-Time Systems, MPSoCs.}
}

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