30 Search Results for "Cherubin, Stefano"

Volume

OASIcs, Volume 107

14th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 12th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms (PARMA-DITAM 2023)

PARMA-DITAM 2023, January 17, 2023, Toulouse, France

Editors: João Bispo, Henri-Pierre Charles, Stefano Cherubin, and Giuseppe Massari

Volume

OASIcs, Volume 100

13th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 11th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms (PARMA-DITAM 2022)

PARMA-DITAM 2022, June 22, 2022, Budapest, Hungary

Editors: Francesca Palumbo, João Bispo, and Stefano Cherubin

Volume

OASIcs, Volume 88

12th Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures and 10th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms (PARMA-DITAM 2021)

PARMA-DITAM 2021, January 19, 2021, Budapest, Hungary

Editors: João Bispo, Stefano Cherubin, and José Flich

Document
DOI: 10.4230/OASIcs.PARMA-DITAM.2024.4
Precision Tuning the Rust Memory-Safe Programming Language

Authors: Gabriele Magnani, Lev Denisov, Daniele Cattaneo, Giovanni Agosta, and Stefano Cherubin

Published in: OASIcs, Volume 116, 15th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 13th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms (PARMA-DITAM 2024)

Abstract
Precision tuning is an increasingly common approach for exploiting the tradeoff between energy efficiency or speedup, and accuracy. Its effectiveness is particularly strong whenever the maximum performance must be extracted from a computing system, such as embedded platforms. In these contexts, current engineering practice sees a dominance of memory-unsafe programming languages such as C and C++. However, the unsafe nature of these languages has come under great scrutiny as it leads to significant software vulnerabilities. Hence, safer programming languages which prevent memory-related bugs by design have been proposed as a replacement. Amongst these safer programming languages, one of the most popular has been Rust. In this work we adapt a state-of-the-art precision tuning tool, TAFFO, to operate on Rust code. By porting the PolyBench/C benchmark suite to Rust, we show that the effectiveness of the precision tuning is not affected by the use of a safer programming language, and moreover the safety properties of the language can be successfully preserved. Specifically, using TAFFO and Rust we achieved up to a 15× speedup over the base Rust code, thanks to the use of precision tuning.
Cite as

Gabriele Magnani, Lev Denisov, Daniele Cattaneo, Giovanni Agosta, and Stefano Cherubin. Precision Tuning the Rust Memory-Safe Programming Language. In 15th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 13th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms (PARMA-DITAM 2024). Open Access Series in Informatics (OASIcs), Volume 116, pp. 4:1-4:12, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2024)

Copy BibTex To Clipboard

@InProceedings{magnani_et_al:OASIcs.PARMA-DITAM.2024.4,
  author =	{Magnani, Gabriele and Denisov, Lev and Cattaneo, Daniele and Agosta, Giovanni and Cherubin, Stefano},
  title =	{{Precision Tuning the Rust Memory-Safe Programming Language}},
  booktitle =	{15th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 13th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms (PARMA-DITAM 2024)},
  pages =	{4:1--4:12},
  series =	{Open Access Series in Informatics (OASIcs)},
  ISBN =	{978-3-95977-307-2},
  ISSN =	{2190-6807},
  year =	{2024},
  volume =	{116},
  editor =	{Bispo, Jo\~{a}o and Xydis, Sotirios and Curzel, Serena and Sousa, Lu{\'\i}s Miguel},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.PARMA-DITAM.2024.4},
  URN =		{urn:nbn:de:0030-drops-196989},
  doi =		{10.4230/OASIcs.PARMA-DITAM.2024.4},
  annote =	{Keywords: Approximate Computing, Memory Safety, Precision Tuning}
}
Document
Complete Volume
DOI: 10.4230/OASIcs.PARMA-DITAM.2023
OASIcs, Volume 107, PARMA-DITAM 2023, Complete Volume

Authors: João Bispo, Henri-Pierre Charles, Stefano Cherubin, and Giuseppe Massari

Published in: OASIcs, Volume 107, 14th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 12th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms (PARMA-DITAM 2023)

Abstract
OASIcs, Volume 107, PARMA-DITAM 2023, Complete Volume
Cite as

14th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 12th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms (PARMA-DITAM 2023). Open Access Series in Informatics (OASIcs), Volume 107, pp. 1-98, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2023)

Copy BibTex To Clipboard

@Proceedings{bispo_et_al:OASIcs.PARMA-DITAM.2023,
  title =	{{OASIcs, Volume 107, PARMA-DITAM 2023, Complete Volume}},
  booktitle =	{14th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 12th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms (PARMA-DITAM 2023)},
  pages =	{1--98},
  series =	{Open Access Series in Informatics (OASIcs)},
  ISBN =	{978-3-95977-269-3},
  ISSN =	{2190-6807},
  year =	{2023},
  volume =	{107},
  editor =	{Bispo, Jo\~{a}o and Charles, Henri-Pierre and Cherubin, Stefano and Massari, Giuseppe},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.PARMA-DITAM.2023},
  URN =		{urn:nbn:de:0030-drops-177193},
  doi =		{10.4230/OASIcs.PARMA-DITAM.2023},
  annote =	{Keywords: OASIcs, Volume 107, PARMA-DITAM 2023, Complete Volume}
}
Document
Front Matter
DOI: 10.4230/OASIcs.PARMA-DITAM.2023.0
Front Matter, Table of Contents, Preface, Conference Organization

Authors: João Bispo, Henri-Pierre Charles, Stefano Cherubin, and Giuseppe Massari

Published in: OASIcs, Volume 107, 14th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 12th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms (PARMA-DITAM 2023)

Abstract
Front Matter, Table of Contents, Preface, Conference Organization
Cite as

14th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 12th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms (PARMA-DITAM 2023). Open Access Series in Informatics (OASIcs), Volume 107, pp. 0:i-0:x, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2023)

Copy BibTex To Clipboard

@InProceedings{bispo_et_al:OASIcs.PARMA-DITAM.2023.0,
  author =	{Bispo, Jo\~{a}o and Charles, Henri-Pierre and Cherubin, Stefano and Massari, Giuseppe},
  title =	{{Front Matter, Table of Contents, Preface, Conference Organization}},
  booktitle =	{14th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 12th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms (PARMA-DITAM 2023)},
  pages =	{0:i--0:x},
  series =	{Open Access Series in Informatics (OASIcs)},
  ISBN =	{978-3-95977-269-3},
  ISSN =	{2190-6807},
  year =	{2023},
  volume =	{107},
  editor =	{Bispo, Jo\~{a}o and Charles, Henri-Pierre and Cherubin, Stefano and Massari, Giuseppe},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.PARMA-DITAM.2023.0},
  URN =		{urn:nbn:de:0030-drops-177206},
  doi =		{10.4230/OASIcs.PARMA-DITAM.2023.0},
  annote =	{Keywords: Front Matter, Table of Contents, Preface, Conference Organization}
}
Document
Invited Paper
DOI: 10.4230/OASIcs.PARMA-DITAM.2023.1
ByteNite: A New Business Model for Grid Computing (Invited Paper)

Authors: Fabio Caironi and Niccolò Andrea Castelli

Published in: OASIcs, Volume 107, 14th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 12th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms (PARMA-DITAM 2023)

Abstract
Years and years of technological advancement have paved the way to cloud computing towards Industry 4.0, making it possible for a wide range of cloud solutions to become a reality, bringing innovation and efficiency to business processes and changing our lifestyles. With the benefit of hindsight in a fully digitalized era, have we ever wondered where does cloud computing come from? Furthermore, as the on-premise commercial model shifted to cloud computing with the advent of the internet, what will the increase in worldwide connectivity and the rise of 5G turn the cloud model into? This article describes in a model for a new commercial grid computing implementation, called "ByteNite". We open the paper with the state of the art of the distributed computing models, including an overview of cloud and grid computing, their commonalities and history, and how they are topical in today’s world. We build the foundations of our work through a key insight that triggers powerful implications in connection with the current technologies. We address the new proposed model through a description of the system, its overall functioning, the underlying business concepts and the innovative value proposition. We finally then dive into its architecture and workflow design, delineating its structure and key features, and the chronological phases of its operation.
Cite as

Fabio Caironi and Niccolò Andrea Castelli. ByteNite: A New Business Model for Grid Computing (Invited Paper). In 14th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 12th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms (PARMA-DITAM 2023). Open Access Series in Informatics (OASIcs), Volume 107, pp. 1:1-1:12, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2023)

Copy BibTex To Clipboard

@InProceedings{caironi_et_al:OASIcs.PARMA-DITAM.2023.1,
  author =	{Caironi, Fabio and Castelli, Niccol\`{o} Andrea},
  title =	{{ByteNite: A New Business Model for Grid Computing}},
  booktitle =	{14th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 12th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms (PARMA-DITAM 2023)},
  pages =	{1:1--1:12},
  series =	{Open Access Series in Informatics (OASIcs)},
  ISBN =	{978-3-95977-269-3},
  ISSN =	{2190-6807},
  year =	{2023},
  volume =	{107},
  editor =	{Bispo, Jo\~{a}o and Charles, Henri-Pierre and Cherubin, Stefano and Massari, Giuseppe},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.PARMA-DITAM.2023.1},
  URN =		{urn:nbn:de:0030-drops-177210},
  doi =		{10.4230/OASIcs.PARMA-DITAM.2023.1},
  annote =	{Keywords: Grid Computing, Cloud Computing, Distributed Applications, High-Throughput Computing, dApps, Utility Computing}
}
Document
Invited Paper
DOI: 10.4230/OASIcs.PARMA-DITAM.2023.2
Challenges and Opportunities in C/C++ Source-To-Source Compilation (Invited Paper)

Authors: João Bispo, Nuno Paulino, and Luís Miguel Sousa

Published in: OASIcs, Volume 107, 14th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 12th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms (PARMA-DITAM 2023)

Abstract
The C/C++ compilation stack (Intermediate Representations (IR), compilation passes and backends) is encumbered by a steep learning curve, which we believe can be lowered by complementing it with approaches such as source-to-source compilation. Source-to-source compilation is a technology that is widely used and quite mature in certain programming environments, such as JavaScript, but that faces a low adoption rate in others. In the particular case of C and C++ some of the identified factors include the high complexity of the languages, increased difficulty in building and maintaining C/C++ parsers, or limitations on using source code as an intermediate representation. Additionally, new technologies such as Multi-Level Intermediate Representation (MLIR) have appeared as potential competitors to source-to-source compilers at this level. In this paper, we present what we have identified as current challenges of source-to-source compilation of C and C++, as well as what we consider to be opportunities and possible directions forward. We also present several examples, implemented on top of the Clava source-to-source compiler, that use some of these ideas and techniques to raise the abstraction level of compiler research on complex compiled languages such as C or C++. The examples include automatic parallelization of for loops, high-level synthesis optimisation, hardware/software partitioning with run-time decisions, and automatic insertion of inline assembly for fast prototyping of custom instructions.
Cite as

João Bispo, Nuno Paulino, and Luís Miguel Sousa. Challenges and Opportunities in C/C++ Source-To-Source Compilation (Invited Paper). In 14th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 12th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms (PARMA-DITAM 2023). Open Access Series in Informatics (OASIcs), Volume 107, pp. 2:1-2:15, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2023)

Copy BibTex To Clipboard

@InProceedings{bispo_et_al:OASIcs.PARMA-DITAM.2023.2,
  author =	{Bispo, Jo\~{a}o and Paulino, Nuno and Sousa, Lu{\'\i}s Miguel},
  title =	{{Challenges and Opportunities in C/C++ Source-To-Source Compilation}},
  booktitle =	{14th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 12th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms (PARMA-DITAM 2023)},
  pages =	{2:1--2:15},
  series =	{Open Access Series in Informatics (OASIcs)},
  ISBN =	{978-3-95977-269-3},
  ISSN =	{2190-6807},
  year =	{2023},
  volume =	{107},
  editor =	{Bispo, Jo\~{a}o and Charles, Henri-Pierre and Cherubin, Stefano and Massari, Giuseppe},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.PARMA-DITAM.2023.2},
  URN =		{urn:nbn:de:0030-drops-177225},
  doi =		{10.4230/OASIcs.PARMA-DITAM.2023.2},
  annote =	{Keywords: Source-to-source, compilation, transpilers, C/C++, code transformation}
}
Document
Invited Paper
DOI: 10.4230/OASIcs.PARMA-DITAM.2023.3
RUST-Encoded Stream Ciphers on a RISC-V Parallel Ultra-Low-Power Processor (Invited Paper)

Authors: Francesco Barchi, Giacomo Pasini, Emanuele Parisi, Giuseppe Tagliavini, Andrea Bartolini, and Andrea Acquaviva

Published in: OASIcs, Volume 107, 14th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 12th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms (PARMA-DITAM 2023)

Abstract
Nowadays, the development of security applications is a relevant topic in the Internet of Things (IoT) and cyber-physical systems (CPS) fields. Different embedded architectures have been adopted in these areas, but the RISC-V parallel ultra-low-power (PULP) architecture stands out as a particularly efficient system. However, it has never been proposed to enable cryptography. In the context of video stream security, stream ciphers enable an efficient solution to ensure data privacy, and the exploitation of the PULP multi-core accelerator cluster paves the way to an efficient implementation of these ciphers. In this paper, we exploit the capability of the PULP architecture coupled with the code safety provided by the RUST programming language to design and implement an efficient stream encryption algorithm. We present a wrapper system between the development libraries of a PULP platform enabling the secure execution of a verified RUST-written implementation of ChaCha20 and AES-CTR, targeting a microdrones based video surveillance system. Experimental tests have resulted in an encryption efficiency of ChaCha20 of 2.3 cycles per Byte (cB), placing the resulting implementation at the state-of-the-art, in direct competition with higher-class architectures like Apple M1 (2.0 cB).
Cite as

Francesco Barchi, Giacomo Pasini, Emanuele Parisi, Giuseppe Tagliavini, Andrea Bartolini, and Andrea Acquaviva. RUST-Encoded Stream Ciphers on a RISC-V Parallel Ultra-Low-Power Processor (Invited Paper). In 14th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 12th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms (PARMA-DITAM 2023). Open Access Series in Informatics (OASIcs), Volume 107, pp. 3:1-3:12, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2023)

Copy BibTex To Clipboard

@InProceedings{barchi_et_al:OASIcs.PARMA-DITAM.2023.3,
  author =	{Barchi, Francesco and Pasini, Giacomo and Parisi, Emanuele and Tagliavini, Giuseppe and Bartolini, Andrea and Acquaviva, Andrea},
  title =	{{RUST-Encoded Stream Ciphers on a RISC-V Parallel Ultra-Low-Power Processor}},
  booktitle =	{14th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 12th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms (PARMA-DITAM 2023)},
  pages =	{3:1--3:12},
  series =	{Open Access Series in Informatics (OASIcs)},
  ISBN =	{978-3-95977-269-3},
  ISSN =	{2190-6807},
  year =	{2023},
  volume =	{107},
  editor =	{Bispo, Jo\~{a}o and Charles, Henri-Pierre and Cherubin, Stefano and Massari, Giuseppe},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.PARMA-DITAM.2023.3},
  URN =		{urn:nbn:de:0030-drops-177232},
  doi =		{10.4230/OASIcs.PARMA-DITAM.2023.3},
  annote =	{Keywords: Parallel Low-Power Embedded Systems, Rust, RISC-V, Stream Cipher}
}
Document
DOI: 10.4230/OASIcs.PARMA-DITAM.2023.4
An Evaluation of the State-Of-The-Art Software and Hardware Implementations of BIKE

Authors: Andrea Galimberti, Gabriele Montanaro, William Fornaciari, and Davide Zoni

Published in: OASIcs, Volume 107, 14th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 12th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms (PARMA-DITAM 2023)

Abstract
NIST is conducting a process for the standardization of post-quantum cryptosystems, i.e., cryptosystems that are resistant to attacks by both traditional and quantum computers and that can thus substitute the traditional public-key cryptography solutions which are expected to be broken by quantum computers in the next decades. This manuscript provides an overview and a comparison of the existing state-of-the-art implementations of the BIKE QC-MDPC code-based post-quantum KEM, a candidate in NIST’s PQC standardization process. We consider both software, hardware, and mixed hardware-software implementations and evaluate their performance and, for hardware ones, their resource utilization.
Cite as

Andrea Galimberti, Gabriele Montanaro, William Fornaciari, and Davide Zoni. An Evaluation of the State-Of-The-Art Software and Hardware Implementations of BIKE. In 14th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 12th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms (PARMA-DITAM 2023). Open Access Series in Informatics (OASIcs), Volume 107, pp. 4:1-4:12, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2023)

Copy BibTex To Clipboard

@InProceedings{galimberti_et_al:OASIcs.PARMA-DITAM.2023.4,
  author =	{Galimberti, Andrea and Montanaro, Gabriele and Fornaciari, William and Zoni, Davide},
  title =	{{An Evaluation of the State-Of-The-Art Software and Hardware Implementations of BIKE}},
  booktitle =	{14th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 12th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms (PARMA-DITAM 2023)},
  pages =	{4:1--4:12},
  series =	{Open Access Series in Informatics (OASIcs)},
  ISBN =	{978-3-95977-269-3},
  ISSN =	{2190-6807},
  year =	{2023},
  volume =	{107},
  editor =	{Bispo, Jo\~{a}o and Charles, Henri-Pierre and Cherubin, Stefano and Massari, Giuseppe},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.PARMA-DITAM.2023.4},
  URN =		{urn:nbn:de:0030-drops-177249},
  doi =		{10.4230/OASIcs.PARMA-DITAM.2023.4},
  annote =	{Keywords: Post-quantum cryptography, QC-MDPC code-based cryptography, BIKE, software execution, hardware acceleration, hardware-software co-design, performance evaluation}
}
Document
DOI: 10.4230/OASIcs.PARMA-DITAM.2023.5
MonTM: Monitoring-Based Thermal Management for Mixed-Criticality Systems

Authors: Marcel Mettler, Martin Rapp, Heba Khdr, Daniel Mueller-Gritschneder, Jörg Henkel, and Ulf Schlichtmann

Published in: OASIcs, Volume 107, 14th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 12th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms (PARMA-DITAM 2023)

Abstract
With a rapidly growing functionality of embedded real-time applications, it becomes inevitable to integrate tasks of different safety integrity levels on one many-core processor leading to a large-scale mixed-criticality system. In this process, it is not sufficient to only isolate shared architectural resources, as different tasks executing on different cores also possibly interfere via the many-core processor’s thermal management. This can possibly lead to best-effort tasks causing deadline violations for safety-critical tasks. In order to prevent such a scenario, we propose a monitoring-based hardware extension that communicates imminent thermal violations between cores via a lightweight interconnect. Building on this infrastructure, we propose a thermal strategy such that best-effort tasks can be throttled in favor of safety-critical tasks. Furthermore, assigning static voltage/frequency (V/f) levels to each safety-critical task based on their worst-case execution time may result in unnecessary high V/f levels when the actual execution finishes faster. To free the otherwise wasted thermal resources, our solution monitors the progress of safety-critical tasks to detect slack and safely reduce their V/f levels. This increases the thermal headroom for best-effort tasks, boosting their performance. In our evaluation, we demonstrate our approach on an 80-core processor to show that it satisfies the thermal and deadline requirements, and simultaneously reduces the run-time of best-effort tasks by up to 45% compared to the state of the art.
Cite as

Marcel Mettler, Martin Rapp, Heba Khdr, Daniel Mueller-Gritschneder, Jörg Henkel, and Ulf Schlichtmann. MonTM: Monitoring-Based Thermal Management for Mixed-Criticality Systems. In 14th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 12th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms (PARMA-DITAM 2023). Open Access Series in Informatics (OASIcs), Volume 107, pp. 5:1-5:12, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2023)

Copy BibTex To Clipboard

@InProceedings{mettler_et_al:OASIcs.PARMA-DITAM.2023.5,
  author =	{Mettler, Marcel and Rapp, Martin and Khdr, Heba and Mueller-Gritschneder, Daniel and Henkel, J\"{o}rg and Schlichtmann, Ulf},
  title =	{{MonTM: Monitoring-Based Thermal Management for Mixed-Criticality Systems}},
  booktitle =	{14th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 12th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms (PARMA-DITAM 2023)},
  pages =	{5:1--5:12},
  series =	{Open Access Series in Informatics (OASIcs)},
  ISBN =	{978-3-95977-269-3},
  ISSN =	{2190-6807},
  year =	{2023},
  volume =	{107},
  editor =	{Bispo, Jo\~{a}o and Charles, Henri-Pierre and Cherubin, Stefano and Massari, Giuseppe},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.PARMA-DITAM.2023.5},
  URN =		{urn:nbn:de:0030-drops-177250},
  doi =		{10.4230/OASIcs.PARMA-DITAM.2023.5},
  annote =	{Keywords: Dynamic thermal management, mixed-criticality, monitoring}
}
Document
DOI: 10.4230/OASIcs.PARMA-DITAM.2023.6
Dynamic Power Consumption of the Full Posit Processing Unit: Analysis and Experiments

Authors: Michele Piccoli, Davide Zoni, William Fornaciari, Giuseppe Massari, Marco Cococcioni, Federico Rossi, Sergio Saponara, and Emanuele Ruffaldi

Published in: OASIcs, Volume 107, 14th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 12th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms (PARMA-DITAM 2023)

Abstract
Since its introduction in 2017, the Posit™ format for representing real numbers has attracted a lot of interest, as an alternative to IEEE 754 floating point representation. Several hardware implementations of arithmetic operations between posit numbers have also been proposed in recent years. In this work, we analyze the dynamic power consumption of the Full Posit Processing Unit (FPPU) recently developed at the University of Pisa. Experimental results show that we can model the dynamic power consumption of the FPPU with an acceptable approximation error from 2.84% (32-bit FPPU) to 7.32% (8-bit FPPU). Furthermore, from the synthesis of the power monitoring unit alongside the FPPU we demonstrate that the additional power module has an area cost that goes from ∼5% (32-bit FPPU) to ∼30% (8-bit FPPU) of the total unit area occupation.
Cite as

Michele Piccoli, Davide Zoni, William Fornaciari, Giuseppe Massari, Marco Cococcioni, Federico Rossi, Sergio Saponara, and Emanuele Ruffaldi. Dynamic Power Consumption of the Full Posit Processing Unit: Analysis and Experiments. In 14th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 12th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms (PARMA-DITAM 2023). Open Access Series in Informatics (OASIcs), Volume 107, pp. 6:1-6:11, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2023)

Copy BibTex To Clipboard

@InProceedings{piccoli_et_al:OASIcs.PARMA-DITAM.2023.6,
  author =	{Piccoli, Michele and Zoni, Davide and Fornaciari, William and Massari, Giuseppe and Cococcioni, Marco and Rossi, Federico and Saponara, Sergio and Ruffaldi, Emanuele},
  title =	{{Dynamic Power Consumption of the Full Posit Processing Unit: Analysis and Experiments}},
  booktitle =	{14th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 12th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms (PARMA-DITAM 2023)},
  pages =	{6:1--6:11},
  series =	{Open Access Series in Informatics (OASIcs)},
  ISBN =	{978-3-95977-269-3},
  ISSN =	{2190-6807},
  year =	{2023},
  volume =	{107},
  editor =	{Bispo, Jo\~{a}o and Charles, Henri-Pierre and Cherubin, Stefano and Massari, Giuseppe},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.PARMA-DITAM.2023.6},
  URN =		{urn:nbn:de:0030-drops-177268},
  doi =		{10.4230/OASIcs.PARMA-DITAM.2023.6},
  annote =	{Keywords: power estimation, computer arithmetic, posit numbers}
}
Document
DOI: 10.4230/OASIcs.PARMA-DITAM.2023.7
Adjacent LSTM-Based Page Scheduling for Hybrid DRAM/NVM Memory Systems

Authors: Manolis Katsaragakis, Konstantinos Stavrakakis, Dimosthenis Masouros, Lazaros Papadopoulos, and Dimitrios Soudris

Published in: OASIcs, Volume 107, 14th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 12th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms (PARMA-DITAM 2023)

Abstract
Recent advances in memory technologies have led to the rapid growth of hybrid systems that combine traditional DRAM and Non Volatile Memory (NVM) technologies, as the latter provide lower cost per byte, low leakage power and larger capacities than DRAM, while they can guarantee comparable access latency. Such kind of heterogeneous memory systems impose new challenges in terms of page placement and migration among the alternative technologies of the heterogeneous memory system. In this paper, we present a novel approach for efficient page placement on heterogeneous DRAM/NVM systems. We design an adjacent LSTM-based approach for page placement, which strongly relies on page accesses prediction, while sharing knowledge among pages with behavioral similarity. The proposed approach leads up to 65.5% optimized performance compared to existing approaches, while achieving near-optimal results and saving 20.2% energy consumption on average. Moreover, we propose a new page replacement policy, namely clustered-LRU, achieving up to 8.1% optimized performance, compared to the default Least Recently Used (LRU) policy.
Cite as

Manolis Katsaragakis, Konstantinos Stavrakakis, Dimosthenis Masouros, Lazaros Papadopoulos, and Dimitrios Soudris. Adjacent LSTM-Based Page Scheduling for Hybrid DRAM/NVM Memory Systems. In 14th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 12th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms (PARMA-DITAM 2023). Open Access Series in Informatics (OASIcs), Volume 107, pp. 7:1-7:12, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2023)

Copy BibTex To Clipboard

@InProceedings{katsaragakis_et_al:OASIcs.PARMA-DITAM.2023.7,
  author =	{Katsaragakis, Manolis and Stavrakakis, Konstantinos and Masouros, Dimosthenis and Papadopoulos, Lazaros and Soudris, Dimitrios},
  title =	{{Adjacent LSTM-Based Page Scheduling for Hybrid DRAM/NVM Memory Systems}},
  booktitle =	{14th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 12th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms (PARMA-DITAM 2023)},
  pages =	{7:1--7:12},
  series =	{Open Access Series in Informatics (OASIcs)},
  ISBN =	{978-3-95977-269-3},
  ISSN =	{2190-6807},
  year =	{2023},
  volume =	{107},
  editor =	{Bispo, Jo\~{a}o and Charles, Henri-Pierre and Cherubin, Stefano and Massari, Giuseppe},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.PARMA-DITAM.2023.7},
  URN =		{urn:nbn:de:0030-drops-177278},
  doi =		{10.4230/OASIcs.PARMA-DITAM.2023.7},
  annote =	{Keywords: Page Placement, Long Short-Term Memory, LSTM, Prediction, NVM, DRAM}
}
Document
DOI: 10.4230/OASIcs.NG-RES.2022.4
Ahead-Of-Real-Time (ART): A Methodology for Static Reduction of Worst-Case Execution Time

Authors: Daniele Cattaneo, Gabriele Magnani, Stefano Cherubin, and Giovanni Agosta

Published in: OASIcs, Volume 98, Third Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2022)

Abstract
Precision tuning is an approximate computing technique for trading precision with lower execution time, and it has been increasingly important in embedded and high-performance computing applications. In particular, embedded applications benefit from lower precision in order to reduce or remove the dependency on computationally-expensive data types such as floating point. Amongst such applications, an important fraction are mission-critical tasks, such as control systems for vehicles or medical use-cases. In this context, the usefulness of precision tuning is limited by concerns about verificability of real-time and quality-of-service constraints. However, with the introduction of optimisations techniques based on integer linear programming and rigorous WCET (Worst-Case Execution Time) models, these constraints not only can be verified automatically, but it becomes possible to use precision tuning to automatically enforce these constraints even when not previously possible. In this work, we show how to combine precision tuning with WCET analysis to enforce a limit on the execution time by using a constraint-based code optimisation pass with a state-of-the-art precision tuning framework.
Cite as

Daniele Cattaneo, Gabriele Magnani, Stefano Cherubin, and Giovanni Agosta. Ahead-Of-Real-Time (ART): A Methodology for Static Reduction of Worst-Case Execution Time. In Third Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2022). Open Access Series in Informatics (OASIcs), Volume 98, pp. 4:1-4:10, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2022)

Copy BibTex To Clipboard

@InProceedings{cattaneo_et_al:OASIcs.NG-RES.2022.4,
  author =	{Cattaneo, Daniele and Magnani, Gabriele and Cherubin, Stefano and Agosta, Giovanni},
  title =	{{Ahead-Of-Real-Time (ART): A Methodology for Static Reduction of Worst-Case Execution Time}},
  booktitle =	{Third Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2022)},
  pages =	{4:1--4:10},
  series =	{Open Access Series in Informatics (OASIcs)},
  ISBN =	{978-3-95977-221-1},
  ISSN =	{2190-6807},
  year =	{2022},
  volume =	{98},
  editor =	{Bertogna, Marko and Terraneo, Federico and Reghenzani, Federico},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.NG-RES.2022.4},
  URN =		{urn:nbn:de:0030-drops-161120},
  doi =		{10.4230/OASIcs.NG-RES.2022.4},
  annote =	{Keywords: Approximate Computing, Precision Tuning, Worst-Case Execution Time}
}
Document
Complete Volume
DOI: 10.4230/OASIcs.PARMA-DITAM.2022
OASIcs, Volume 100, PARMA-DITAM 2022, Complete Volume

Authors: Francesca Palumbo, João Bispo, and Stefano Cherubin

Published in: OASIcs, Volume 100, 13th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 11th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms (PARMA-DITAM 2022)

Abstract
OASIcs, Volume 100, PARMA-DITAM 2022, Complete Volume
Cite as

13th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 11th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms (PARMA-DITAM 2022). Open Access Series in Informatics (OASIcs), Volume 100, pp. 1-104, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2022)

Copy BibTex To Clipboard

@Proceedings{palumbo_et_al:OASIcs.PARMA-DITAM.2022,
  title =	{{OASIcs, Volume 100, PARMA-DITAM 2022, Complete Volume}},
  booktitle =	{13th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 11th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms (PARMA-DITAM 2022)},
  pages =	{1--104},
  series =	{Open Access Series in Informatics (OASIcs)},
  ISBN =	{978-3-95977-231-0},
  ISSN =	{2190-6807},
  year =	{2022},
  volume =	{100},
  editor =	{Palumbo, Francesca and Bispo, Jo\~{a}o and Cherubin, Stefano},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.PARMA-DITAM.2022},
  URN =		{urn:nbn:de:0030-drops-161152},
  doi =		{10.4230/OASIcs.PARMA-DITAM.2022},
  annote =	{Keywords: OASIcs, Volume 100, PARMA-DITAM 2022, Complete Volume}
}
  • Refine by Type
  • 27 Document/PDF
  • 3 Volume

  • Refine by Publication Year
  • 1 2024
  • 10 2023
  • 11 2022
  • 8 2021

  • Refine by Author
  • 8 Cherubin, Stefano
  • 7 Bispo, João
  • 5 Agosta, Giovanni
  • 5 Cattaneo, Daniele
  • 4 Magnani, Gabriele
  • Show More...

  • Refine by Series/Journal
  • 27 OASIcs

  • Refine by Classification
  • 8 Software and its engineering → Compilers
  • 6 Computer systems organization → Multicore architectures
  • 5 Computer systems organization → Reconfigurable computing
  • 4 Software and its engineering → Runtime environments
  • 3 Computer systems organization → Cloud computing
  • Show More...

  • Refine by Keyword
  • 4 Precision Tuning
  • 3 Approximate Computing
  • 3 Conference Organization
  • 3 Front Matter
  • 3 Preface
  • Show More...

Any Issues?
X

Feedback on the Current Page

CAPTCHA

Thanks for your feedback!

Feedback submitted to Dagstuhl Publishing

Could not send message

Please try again later or send an E-mail
© 2023-2025 Schloss Dagstuhl – LZI GmbH About DROPS Imprint Privacy Contact