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Documents authored by Ernst, Rolf

Found 2 Possible Name Variants:

Ernst, Rolf

Document
DOI: 10.4230/LIPIcs.ECRTS.2019.26
Slot-Based Transmission Protocol for Real-Time NoCs - SBT-NoC

Authors: Borislav Nikolić, Robin Hofmann, and Rolf Ernst

Published in: LIPIcs, Volume 133, 31st Euromicro Conference on Real-Time Systems (ECRTS 2019)

Abstract
Network on Chip (NoC) interconnects are some of the most challenging-to-analyse components of multiprocessor platforms. This is primarily due to the following two reasons: (i) NoCs contain numerous shared resources (e.g. routers, links), and (ii) the network traffic often concurrently traverses multiple of those resources. Consequently, complex contention scenarios among traffic flows might occur, some of the important implications being significant performance limitations, and difficulties when performing the real-time analysis. In this work, we propose a slot-based transmission protocol for NoCs (called SBT-NoC), and an accompanying analysis method for deriving worst-case traffic latencies. The cornerstone of SBT-NoC is a contention-less slot-based transmission, arbitrated via a protocol running on a dedicated network medium. The main advantage of SBT-NoC is that, while not requiring any sophisticated hardware support (e.g. virtual channels, a flit-level arbitration), it makes NoCs amenable to real-time analysis and guarantees bounded low latencies of high-priority time-critical flows, which is a sine qua non for the inclusion of NoCs, and multiprocessors in general, in the real-time domain. The experimental evaluation, including both synthetic workloads and a use-case of an autonomous driving vehicle application, reveals that SBT-NoC offers a plethora of configuration opportunities, which makes it applicable to a wide range of diverse traffic workloads.
Cite as

Borislav Nikolić, Robin Hofmann, and Rolf Ernst. Slot-Based Transmission Protocol for Real-Time NoCs - SBT-NoC. In 31st Euromicro Conference on Real-Time Systems (ECRTS 2019). Leibniz International Proceedings in Informatics (LIPIcs), Volume 133, pp. 26:1-26:22, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2019)

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@InProceedings{nikolic_et_al:LIPIcs.ECRTS.2019.26,
  author =	{Nikoli\'{c}, Borislav and Hofmann, Robin and Ernst, Rolf},
  title =	{{Slot-Based Transmission Protocol for Real-Time NoCs - SBT-NoC}},
  booktitle =	{31st Euromicro Conference on Real-Time Systems (ECRTS 2019)},
  pages =	{26:1--26:22},
  series =	{Leibniz International Proceedings in Informatics (LIPIcs)},
  ISBN =	{978-3-95977-110-8},
  ISSN =	{1868-8969},
  year =	{2019},
  volume =	{133},
  editor =	{Quinton, Sophie},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2019.26},
  URN =		{urn:nbn:de:0030-drops-107633},
  doi =		{10.4230/LIPIcs.ECRTS.2019.26},
  annote =	{Keywords: Real-Time Systems, Embedded Systems, Network-on-Chip, Protocols}
}
Document
Complete Volume
DOI: 10.4230/OASIcs.ASD.2019
OASIcs, Volume 68, ASD'19, Complete Volume

Authors: Selma Saidi, Rolf Ernst, and Dirk Ziegenbein

Published in: OASIcs, Volume 68, Workshop on Autonomous Systems Design (ASD 2019)

Abstract
OASIcs, Volume 68, ASD'19, Complete Volume
Cite as

Workshop on Autonomous Systems Design (ASD 2019). Open Access Series in Informatics (OASIcs), Volume 68, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2019)

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@Proceedings{saidi_et_al:OASIcs.ASD.2019,
  title =	{{OASIcs, Volume 68, ASD'19, Complete Volume}},
  booktitle =	{Workshop on Autonomous Systems Design (ASD 2019)},
  series =	{Open Access Series in Informatics (OASIcs)},
  ISBN =	{978-3-95977-102-3},
  ISSN =	{2190-6807},
  year =	{2019},
  volume =	{68},
  editor =	{Saidi, Selma and Ernst, Rolf and Ziegenbein, Dirk},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.ASD.2019},
  URN =		{urn:nbn:de:0030-drops-103628},
  doi =		{10.4230/OASIcs.ASD.2019},
  annote =	{Keywords: Hardware, Analysis and design of emerging devices and systems, Computer systems organization, Robotic autonomy, Software and its engineering, Software safety, Dependable and fault-tolerant systems and networks}
}
Document
Front Matter
DOI: 10.4230/OASIcs.ASD.2019.0
Front Matter, Table of Contents, Preface, Conference Organization

Authors: Selma Saidi, Rolf Ernst, and Dirk Ziegenbein

Published in: OASIcs, Volume 68, Workshop on Autonomous Systems Design (ASD 2019)

Abstract
Front Matter, Table of Contents, Preface, Conference Organization
Cite as

Workshop on Autonomous Systems Design (ASD 2019). Open Access Series in Informatics (OASIcs), Volume 68, pp. 0:i-0:xviii, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2019)

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@InProceedings{saidi_et_al:OASIcs.ASD.2019.0,
  author =	{Saidi, Selma and Ernst, Rolf and Ziegenbein, Dirk},
  title =	{{Front Matter, Table of Contents, Preface, Conference Organization}},
  booktitle =	{Workshop on Autonomous Systems Design (ASD 2019)},
  pages =	{0:i--0:xviii},
  series =	{Open Access Series in Informatics (OASIcs)},
  ISBN =	{978-3-95977-102-3},
  ISSN =	{2190-6807},
  year =	{2019},
  volume =	{68},
  editor =	{Saidi, Selma and Ernst, Rolf and Ziegenbein, Dirk},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.ASD.2019.0},
  URN =		{urn:nbn:de:0030-drops-103337},
  doi =		{10.4230/OASIcs.ASD.2019.0},
  annote =	{Keywords: Front Matter, Table of Contents, Preface, Conference Organization}
}
Document
DOI: 10.4230/OASIcs.ASD.2019.4
Controlling Concurrent Change - A Multiview Approach Toward Updatable Vehicle Automation Systems

Authors: Mischa Möstl, Marcus Nolte, Johannes Schlatow, and Rolf Ernst

Published in: OASIcs, Volume 68, Workshop on Autonomous Systems Design (ASD 2019)

Abstract
The development of SAE Level 3+ vehicles [{SAE}, 2014] poses new challenges not only for the functional development, but also for design and development processes. Such systems consist of a growing number of interconnected functional, as well as hardware and software components, making safety design increasingly difficult. In order to cope with emergent behavior at the vehicle level, thorough systems engineering becomes a key requirement, which enables traceability between different design viewpoints. Ensuring traceability is a key factor towards an efficient validation and verification of such systems. Formal models can in turn assist in keeping track of how the different viewpoints relate to each other and how the interplay of components affects the overall system behavior. Based on experience from the project Controlling Concurrent Change, this paper presents an approach towards model-based integration and verification of a cause effect chain for a component-based vehicle automation system. It reasons on a cross-layer model of the resulting system, which covers necessary aspects of a design in individual architectural views, e.g. safety and timing. In the synthesis stage of integration, our approach is capable of inserting enforcement mechanisms into the design to ensure adherence to the model. We present a use case description for an environment perception system, starting with a functional architecture, which is the basis for componentization of the cause effect chain. By tying the vehicle architecture to the cross-layer integration model, we are able to map the reasoning done during verification to vehicle behavior.
Cite as

Mischa Möstl, Marcus Nolte, Johannes Schlatow, and Rolf Ernst. Controlling Concurrent Change - A Multiview Approach Toward Updatable Vehicle Automation Systems. In Workshop on Autonomous Systems Design (ASD 2019). Open Access Series in Informatics (OASIcs), Volume 68, pp. 4:1-4:15, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2019)

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@InProceedings{mostl_et_al:OASIcs.ASD.2019.4,
  author =	{M\"{o}stl, Mischa and Nolte, Marcus and Schlatow, Johannes and Ernst, Rolf},
  title =	{{Controlling Concurrent Change - A Multiview Approach Toward Updatable Vehicle Automation Systems}},
  booktitle =	{Workshop on Autonomous Systems Design (ASD 2019)},
  pages =	{4:1--4:15},
  series =	{Open Access Series in Informatics (OASIcs)},
  ISBN =	{978-3-95977-102-3},
  ISSN =	{2190-6807},
  year =	{2019},
  volume =	{68},
  editor =	{Saidi, Selma and Ernst, Rolf and Ziegenbein, Dirk},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.ASD.2019.4},
  URN =		{urn:nbn:de:0030-drops-103376},
  doi =		{10.4230/OASIcs.ASD.2019.4},
  annote =	{Keywords: safety, behavior, functional, architecture, multi-view, automated driving}
}
Document
DOI: 10.4230/DagRep.8.2.122
The Logical Execution Time Paradigm: New Perspectives for Multicore Systems (Dagstuhl Seminar 18092)

Authors: Rolf Ernst, Stefan Kuntz, Sophie Quinton, and Martin Simons

Published in: Dagstuhl Reports, Volume 8, Issue 2 (2018)

Abstract
This report documents the program and the outcomes of Dagstuhl Seminar 18092 "The Logical Execution Time Paradigm: New Perspectives for Multicore Systems". The seminar brought together academic and industrial researchers working on challenges related to the Logical Execution Time Paradigm (LET). The main purpose was to promote a closer interaction between the sub-communities involved in the application of LET to multicore systems, with a particular emphasis on the automotive domain.
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Rolf Ernst, Stefan Kuntz, Sophie Quinton, and Martin Simons. The Logical Execution Time Paradigm: New Perspectives for Multicore Systems (Dagstuhl Seminar 18092). In Dagstuhl Reports, Volume 8, Issue 2, pp. 122-149, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2018)

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@Article{ernst_et_al:DagRep.8.2.122,
  author =	{Ernst, Rolf and Kuntz, Stefan and Quinton, Sophie and Simons, Martin},
  title =	{{The Logical Execution Time Paradigm: New Perspectives for Multicore Systems (Dagstuhl Seminar 18092)}},
  pages =	{122--149},
  journal =	{Dagstuhl Reports},
  ISSN =	{2192-5283},
  year =	{2018},
  volume =	{8},
  number =	{2},
  editor =	{Ernst, Rolf and Kuntz, Stefan and Quinton, Sophie and Simons, Martin},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/DagRep.8.2.122},
  URN =		{urn:nbn:de:0030-drops-92939},
  doi =		{10.4230/DagRep.8.2.122},
  annote =	{Keywords: Automotive domain, logical execution time, multicore architectures, real-time systems}
}
Document
DOI: 10.4230/LIPIcs.ECRTS.2018.15
Verifying Weakly-Hard Real-Time Properties of Traffic Streams in Switched Networks

Authors: Leonie Ahrendts, Sophie Quinton, Thomas Boroske, and Rolf Ernst

Published in: LIPIcs, Volume 106, 30th Euromicro Conference on Real-Time Systems (ECRTS 2018)

Abstract
In this paper, we introduce the first verification method which is able to provide weakly-hard real-time guarantees for tasks and task chains in systems with multiple resources under partitioned scheduling with fixed priorities. Existing weakly-hard real-time verification techniques are restricted today to systems with a single resource. A weakly-hard real-time guarantee specifies an upper bound on the maximum number m of deadline misses of a task in a sequence of k consecutive executions. Such a guarantee is useful if a task can experience a bounded number of deadline misses without impacting the system mission. We present our verification method in the context of switched networks with traffic streams between nodes, and demonstrate its practical applicability in an automotive case study.
Cite as

Leonie Ahrendts, Sophie Quinton, Thomas Boroske, and Rolf Ernst. Verifying Weakly-Hard Real-Time Properties of Traffic Streams in Switched Networks. In 30th Euromicro Conference on Real-Time Systems (ECRTS 2018). Leibniz International Proceedings in Informatics (LIPIcs), Volume 106, pp. 15:1-15:22, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2018)

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@InProceedings{ahrendts_et_al:LIPIcs.ECRTS.2018.15,
  author =	{Ahrendts, Leonie and Quinton, Sophie and Boroske, Thomas and Ernst, Rolf},
  title =	{{Verifying Weakly-Hard Real-Time Properties of Traffic Streams in Switched Networks}},
  booktitle =	{30th Euromicro Conference on Real-Time Systems (ECRTS 2018)},
  pages =	{15:1--15:22},
  series =	{Leibniz International Proceedings in Informatics (LIPIcs)},
  ISBN =	{978-3-95977-075-0},
  ISSN =	{1868-8969},
  year =	{2018},
  volume =	{106},
  editor =	{Altmeyer, Sebastian},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2018.15},
  URN =		{urn:nbn:de:0030-drops-89879},
  doi =		{10.4230/LIPIcs.ECRTS.2018.15},
  annote =	{Keywords: embedded and cyber-physical systems, weakly-hard real-time systems and networks, timing analysis}
}
Document
DOI: 10.4230/LIPIcs.ECRTS.2017.17
Budgeting Under-Specified Tasks for Weakly-Hard Real-Time Systems

Authors: Zain A. H. Hammadeh, Sophie Quinton, Marco Panunzio, Rafik Henia, Laurent Rioux, and Rolf Ernst

Published in: LIPIcs, Volume 76, 29th Euromicro Conference on Real-Time Systems (ECRTS 2017)

Abstract
In this paper, we present an extension of slack analysis for budgeting in the design of weakly-hard real-time systems. During design, it often happens that some parts of a task set are fully specified while other parameters, e.g. regarding recovery or monitoring tasks, will be available only much later. In such cases, slack analysis can help anticipate how these missing parameters can influence the behavior of the whole system so that a resource budget can be allocated to them. It is, however, sufficient in many application contexts to budget these tasks in order to preserve weakly-hard rather than hard guarantees. We thus present an extension of slack analysis for deriving task budgets for systems with hard and weakly-hard requirements. This work is motivated by and validated on a realistic case study inspired by industrial practice.
Cite as

Zain A. H. Hammadeh, Sophie Quinton, Marco Panunzio, Rafik Henia, Laurent Rioux, and Rolf Ernst. Budgeting Under-Specified Tasks for Weakly-Hard Real-Time Systems. In 29th Euromicro Conference on Real-Time Systems (ECRTS 2017). Leibniz International Proceedings in Informatics (LIPIcs), Volume 76, pp. 17:1-17:22, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2017)

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@InProceedings{hammadeh_et_al:LIPIcs.ECRTS.2017.17,
  author =	{Hammadeh, Zain A. H. and Quinton, Sophie and Panunzio, Marco and Henia, Rafik and Rioux, Laurent and Ernst, Rolf},
  title =	{{Budgeting Under-Specified Tasks for Weakly-Hard Real-Time Systems}},
  booktitle =	{29th Euromicro Conference on Real-Time Systems (ECRTS 2017)},
  pages =	{17:1--17:22},
  series =	{Leibniz International Proceedings in Informatics (LIPIcs)},
  ISBN =	{978-3-95977-037-8},
  ISSN =	{1868-8969},
  year =	{2017},
  volume =	{76},
  editor =	{Bertogna, Marko},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2017.17},
  URN =		{urn:nbn:de:0030-drops-71636},
  doi =		{10.4230/LIPIcs.ECRTS.2017.17},
  annote =	{Keywords: Real-time, Weakly-hard, Slack analysis, Execution budget, Fixed priority}
}
Document
DOI: 10.4230/LIPIcs.ECRTS.2017.20
Replica-Aware Co-Scheduling for Mixed-Criticality

Authors: Eberle A. Rambo and Rolf Ernst

Published in: LIPIcs, Volume 76, 29th Euromicro Conference on Real-Time Systems (ECRTS 2017)

Abstract
Cross-layer fault-tolerance solutions are the key to effectively and efficiently increase the reliability in future safety-critical real-time systems. Replicated software execution with hardware support for error detection is a cross-layer approach that exploits future many-core platforms to increase reliability without resorting to redundancy in hardware. The performance of such systems, however, strongly depends on the scheduler. Standard schedulers, such as Partitioned~Strict Priority Preemptive (SPP) and Time-Division Multiplexing (TDM)-based ones, although widely employed, provide poor performance in face of replicated execution. In this paper, we propose the replica-aware co-scheduling for mixed-critical systems. Experimental results show schedulability improvements of more than 1.5x when compared to TDM and 6.9x when compared to SPP.
Cite as

Eberle A. Rambo and Rolf Ernst. Replica-Aware Co-Scheduling for Mixed-Criticality. In 29th Euromicro Conference on Real-Time Systems (ECRTS 2017). Leibniz International Proceedings in Informatics (LIPIcs), Volume 76, pp. 20:1-20:20, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2017)

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@InProceedings{rambo_et_al:LIPIcs.ECRTS.2017.20,
  author =	{Rambo, Eberle A. and Ernst, Rolf},
  title =	{{Replica-Aware Co-Scheduling for Mixed-Criticality}},
  booktitle =	{29th Euromicro Conference on Real-Time Systems (ECRTS 2017)},
  pages =	{20:1--20:20},
  series =	{Leibniz International Proceedings in Informatics (LIPIcs)},
  ISBN =	{978-3-95977-037-8},
  ISSN =	{1868-8969},
  year =	{2017},
  volume =	{76},
  editor =	{Bertogna, Marko},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2017.20},
  URN =		{urn:nbn:de:0030-drops-71529},
  doi =		{10.4230/LIPIcs.ECRTS.2017.20},
  annote =	{Keywords: replicated execution, scheduling, fault-tolerance, real-time systems}
}
Document
DOI: 10.4230/OASIcs.WCET.2005.813
Analysis of Memory Latencies in Multi-Processor Systems

Authors: Jan Stachulat, Simon Schliecker, Matthias Ivers, and Rolf Ernst

Published in: OASIcs, Volume 1, 5th International Workshop on Worst-Case Execution Time Analysis (WCET'05) (2007)

Abstract
Predicting timing behavior is key to efficient embedded real-time system design and verification. Current approaches to determine end-to-end latencies in parallel heterogeneous architectures focus on performance analysis either on task or system level. Especially memory accesses, basic operations of embedded application, cannot be accurately captured on a single level alone: While task level methods simplify system behavior, system level methods simplify task behavior. Both perspectives lead to overly pessimistic estimations. To tackle these complex interactions we integrate task and system level analysis. Each analysis level is provided with the necessary data to allow precise computations, while adequate abstraction prevents high time complexity.
Cite as

Jan Stachulat, Simon Schliecker, Matthias Ivers, and Rolf Ernst. Analysis of Memory Latencies in Multi-Processor Systems. In 5th International Workshop on Worst-Case Execution Time Analysis (WCET'05). Open Access Series in Informatics (OASIcs), Volume 1, pp. 33-36, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2007)

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@InProceedings{stachulat_et_al:OASIcs.WCET.2005.813,
  author =	{Stachulat, Jan and Schliecker, Simon and Ivers, Matthias and Ernst, Rolf},
  title =	{{Analysis of Memory Latencies in Multi-Processor Systems}},
  booktitle =	{5th International Workshop on Worst-Case Execution Time Analysis (WCET'05)},
  pages =	{33--36},
  series =	{Open Access Series in Informatics (OASIcs)},
  ISBN =	{978-3-939897-24-8},
  ISSN =	{2190-6807},
  year =	{2007},
  volume =	{1},
  editor =	{Wilhelm, Reinhard},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.WCET.2005.813},
  URN =		{urn:nbn:de:0030-drops-8130},
  doi =		{10.4230/OASIcs.WCET.2005.813},
  annote =	{Keywords: Multi-processor Performance Analysis, Memory Access Latency, Worst Case Execution Time}
}
Document
DOI: 10.4230/DagSemProc.06141.9
FlexFilm - an Image Processor for Digital Film Processing

Authors: Sven Heithecker, Amilcar do Carmo Lucas, and Rolf Ernst

Published in: Dagstuhl Seminar Proceedings, Volume 6141, Dynamically Reconfigurable Architectures (2006)

Abstract
Digital film processing is characterized by a resolution of at least 2K (2048x1536 pixels per frame at 30 bit/pixel and 24 pictures/s, data rate of 2.2 GBit/s); higher resolutions of 4K (8.8 GBit/s) and even 8K (35.2 GBit/s) are on their way. Real-time processing at this data rate is beyond the scope of today's standard and DSP processors, and ASICs are not economically viable due to the small market volume. Therefore, an FPGA-based approach was followed in the FlexFilm project. Different applications are supported on a single hardware platform by using different FPGA configurations. The multi-board, multi-FPGA hardware/software architecture is based on Xilinx Virtex-II Pro FPGAs which contain the reconfigurable image stream processing data path, large SDRAM memories for multiple frame storage and a PCI express communication backbone network. The FPGA-embedded CPU is used for control and less computation intensive tasks. This paper will focus on three key aspects: a) the used design methodology which combines macro component configuration and macro-level floorplanning with weak programmability using distributed microcoding, b) the global communication framework with communication scheduling and c) the configurable, multi-stream scheduling SDRAM controller with QoS support by access prioritization and traffic shaping. As an example, a complex noise reduction algorithm including a 2.5 dimensions DWT and a full 16x16 motion estimation at 24 fps requiring a total of 203 Gops/s net computing performance and a total of 28 Gbit/s DDR-SDRAM frame memory bandwidth will be shown.
Cite as

Sven Heithecker, Amilcar do Carmo Lucas, and Rolf Ernst. FlexFilm - an Image Processor for Digital Film Processing. In Dynamically Reconfigurable Architectures. Dagstuhl Seminar Proceedings, Volume 6141, pp. 1-11, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2006)

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@InProceedings{heithecker_et_al:DagSemProc.06141.9,
  author =	{Heithecker, Sven and do Carmo Lucas, Amilcar and Ernst, Rolf},
  title =	{{FlexFilm - an Image Processor for Digital Film Processing}},
  booktitle =	{Dynamically Reconfigurable Architectures},
  pages =	{1--11},
  series =	{Dagstuhl Seminar Proceedings (DagSemProc)},
  ISSN =	{1862-4405},
  year =	{2006},
  volume =	{6141},
  editor =	{Peter M. Athanas and J\"{u}rgen Becker and Gordon Brebner and J\"{u}rgen Teich},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/DagSemProc.06141.9},
  URN =		{urn:nbn:de:0030-drops-7377},
  doi =		{10.4230/DagSemProc.06141.9},
  annote =	{Keywords: Digital film, FPGA, reconfigurable, stream-based architechture, weak programming, SDRAM-controller, QoS, communication centric, communication scheduli}
}
Document
DOI: 10.4230/OASIcs.WCET.2006.676
A Framework for the Busy Time Calculation of Multiple Correlated Events

Authors: Simon Schliecker, Matthias Ivers, Jan Staschulat, and Rolf Ernst

Published in: OASIcs, Volume 4, 6th International Workshop on Worst-Case Execution Time Analysis (WCET'06) (2006)

Abstract
Many approaches to determine the response time of a task have difficulty to model tasks with multiple memory or coprocessor accesses with variable access times during the execution. As the request times highly depend on system setup and state, they can not be trivially bounded. If they are bounded by a constant value, large discrepancies between average and worst case make the focus on single worst cases vulnerable to overestimation. We present a novel approach to include remote busy time in the execution time analysis of tasks. We determine the time for multiple requests by a task efficiently and and far less conservative than previous approaches. These requests may be disturbed by other events in the system. We show how to integrate such a multiple event busy time analysis to take into account behavior of tasks that voluntarily suspend themselves and require multiple data from remote parts of the system.
Cite as

Simon Schliecker, Matthias Ivers, Jan Staschulat, and Rolf Ernst. A Framework for the Busy Time Calculation of Multiple Correlated Events. In 6th International Workshop on Worst-Case Execution Time Analysis (WCET'06). Open Access Series in Informatics (OASIcs), Volume 4, pp. 1-6, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2006)

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@InProceedings{schliecker_et_al:OASIcs.WCET.2006.676,
  author =	{Schliecker, Simon and Ivers, Matthias and Staschulat, Jan and Ernst, Rolf},
  title =	{{A Framework for the Busy Time Calculation of Multiple Correlated Events}},
  booktitle =	{6th International Workshop on Worst-Case Execution Time Analysis (WCET'06)},
  pages =	{1--6},
  series =	{Open Access Series in Informatics (OASIcs)},
  ISBN =	{978-3-939897-03-3},
  ISSN =	{2190-6807},
  year =	{2006},
  volume =	{4},
  editor =	{Mueller, Frank},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.WCET.2006.676},
  URN =		{urn:nbn:de:0030-drops-6767},
  doi =		{10.4230/OASIcs.WCET.2006.676},
  annote =	{Keywords: Response time analysis, multiple memory accesses, multiprocessor, hard real-time, busy time}
}

Rolf, Ernst

Document
DOI: 10.4230/DagSemRep.239
Mobile Multimedia Communication - Systems and Networks (Dagstuhl Seminar 99061)

Authors: Andrew Campbell, Ernst Rolf, Stephen Pink, and Martina Zitterbart

Published in: Dagstuhl Seminar Reports. Dagstuhl Seminar Reports, Volume 1 (2021)

Abstract
Cite as

Andrew Campbell, Ernst Rolf, Stephen Pink, and Martina Zitterbart. Mobile Multimedia Communication - Systems and Networks (Dagstuhl Seminar 99061). Dagstuhl Seminar Report 239, pp. 1-16, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2001)

Copy BibTex To Clipboard

@TechReport{campbell_et_al:DagSemRep.239,
  author =	{Campbell, Andrew and Rolf, Ernst and Pink, Stephen and Zitterbart, Martina},
  title =	{{Mobile Multimedia Communication - Systems and Networks (Dagstuhl Seminar 99061)}},
  pages =	{1--16},
  ISSN =	{1619-0203},
  year =	{2001},
  type = 	{Dagstuhl Seminar Report},
  number =	{239},
  institution =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/DagSemRep.239},
  URN =		{urn:nbn:de:0030-drops-151253},
  doi =		{10.4230/DagSemRep.239},
}
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