11 Search Results for "Yomsi, Patrick Meumeu"

Volume

OASIcs, Volume 117

Fifth Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2024)

NG-RES 2024, January 17-19, 2024, Munich, Germany

Editors: Patrick Meumeu Yomsi and Stefan Wildermann

Document
Complete Volume
DOI: 10.4230/OASIcs.NG-RES.2024
OASIcs, Volume 117, NG-RES 2024, Complete Volume

Authors: Patrick Meumeu Yomsi and Stefan Wildermann

Published in: OASIcs, Volume 117, Fifth Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2024)

Abstract
OASIcs, Volume 117, NG-RES 2024, Complete Volume
Cite as

Fifth Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2024). Open Access Series in Informatics (OASIcs), Volume 117, pp. 1-62, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2024)

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@Proceedings{yomsi_et_al:OASIcs.NG-RES.2024,
  title =	{{OASIcs, Volume 117, NG-RES 2024, Complete Volume}},
  booktitle =	{Fifth Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2024)},
  pages =	{1--62},
  series =	{Open Access Series in Informatics (OASIcs)},
  ISBN =	{978-3-95977-313-3},
  ISSN =	{2190-6807},
  year =	{2024},
  volume =	{117},
  editor =	{Yomsi, Patrick Meumeu and Wildermann, Stefan},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops-dev.dagstuhl.de/entities/document/10.4230/OASIcs.NG-RES.2024},
  URN =		{urn:nbn:de:0030-drops-197028},
  doi =		{10.4230/OASIcs.NG-RES.2024},
  annote =	{Keywords: OASIcs, Volume 117, NG-RES 2024, Complete Volume}
}
Document
Front Matter
DOI: 10.4230/OASIcs.NG-RES.2024.0
Front Matter, Table of Contents, Preface, Conference Organization

Authors: Patrick Meumeu Yomsi and Stefan Wildermann

Published in: OASIcs, Volume 117, Fifth Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2024)

Abstract
Front Matter, Table of Contents, Preface, Conference Organization
Cite as

Fifth Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2024). Open Access Series in Informatics (OASIcs), Volume 117, pp. 0:i-0:x, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2024)

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@InProceedings{yomsi_et_al:OASIcs.NG-RES.2024.0,
  author =	{Yomsi, Patrick Meumeu and Wildermann, Stefan},
  title =	{{Front Matter, Table of Contents, Preface, Conference Organization}},
  booktitle =	{Fifth Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2024)},
  pages =	{0:i--0:x},
  series =	{Open Access Series in Informatics (OASIcs)},
  ISBN =	{978-3-95977-313-3},
  ISSN =	{2190-6807},
  year =	{2024},
  volume =	{117},
  editor =	{Yomsi, Patrick Meumeu and Wildermann, Stefan},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops-dev.dagstuhl.de/entities/document/10.4230/OASIcs.NG-RES.2024.0},
  URN =		{urn:nbn:de:0030-drops-197032},
  doi =		{10.4230/OASIcs.NG-RES.2024.0},
  annote =	{Keywords: Front Matter, Table of Contents, Preface, Conference Organization}
}
Document
Invited Paper
DOI: 10.4230/OASIcs.NG-RES.2024.1
HMB: Scheduling PREM-Like Real-Time Tasks at High Memory Bandwidth (Invited Paper)

Authors: Mohammadhassan Gholami Derouei, Paolo Valente, Marco Solieri, and Andrea Marongiu

Published in: OASIcs, Volume 117, Fifth Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2024)

Abstract
Current homogeneous and heterogeneous computing systems reach high performance through parallelization. Yet, parallel execution of tasks entails non-trivial latency-vs-throughput issues when it comes to concurrent accesses to shared memory. In this respect, effective bandwidth regulation solutions do exist, and provide a basic mechanism to control the latency of memory accesses. Such solutions, though, are often cumbersome to deploy and to configure to guarantee both bounded latency and high utilization of the memory bandwidth. The problem is that memory latency varies non-linearly with the number and type of concurrent accesses, and the latter may in turn vary with time, often unpredictably. For this reason, previous attempts at memory regulation in scheduling solutions resulted either in poor real-time execution guarantees, or in severe underutilization of the memory bandwidth. In this paper, we outline High Memory Bandwidth (HMB), a scheduling solution that guarantees bounded response times to real-time task sets through memory regulation, while also reaching a high utilization memory bandwidth. Since the complete solution is complex, just like the problem it addresses, this preliminary work defines in full detail only the core mechanism. This mechanism builds on the notion of memory access slowdown experienced by any processor performing back-to-back memory operations; this slowdown is due to the interference generated by other processors also accessing the memory at the same time. The core mechanism assumes that each processor can tolerate a certain amount of slowdown before the timing behavior of the task(s) it is running is compromised. Each processor has a priority assigned: the higher the priority, the more stringent the timing requirements. The slowdown can be controlled by regulating with precision the maximum amount of system bandwidth each processor is allowed to use, based on its priority. The proposed mechanism finds the maximum bandwidth each processor can use such that the highest number of processors simultaneously accessing memory is found (thus avoiding memory bandwidth underutilization) while guaranteeing that the slowdown of each processor is kept within the tolerated limits.
Cite as

Mohammadhassan Gholami Derouei, Paolo Valente, Marco Solieri, and Andrea Marongiu. HMB: Scheduling PREM-Like Real-Time Tasks at High Memory Bandwidth (Invited Paper). In Fifth Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2024). Open Access Series in Informatics (OASIcs), Volume 117, pp. 1:1-1:18, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2024)

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@InProceedings{gholamiderouei_et_al:OASIcs.NG-RES.2024.1,
  author =	{Gholami Derouei, Mohammadhassan and Valente, Paolo and Solieri, Marco and Marongiu, Andrea},
  title =	{{HMB: Scheduling PREM-Like Real-Time Tasks at High Memory Bandwidth}},
  booktitle =	{Fifth Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2024)},
  pages =	{1:1--1:18},
  series =	{Open Access Series in Informatics (OASIcs)},
  ISBN =	{978-3-95977-313-3},
  ISSN =	{2190-6807},
  year =	{2024},
  volume =	{117},
  editor =	{Yomsi, Patrick Meumeu and Wildermann, Stefan},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops-dev.dagstuhl.de/entities/document/10.4230/OASIcs.NG-RES.2024.1},
  URN =		{urn:nbn:de:0030-drops-197049},
  doi =		{10.4230/OASIcs.NG-RES.2024.1},
  annote =	{Keywords: Heterogenous systems, Parallel execution, Shared memory, Bandwidth regulation, Memory access, Real-time execution, Memory bandwidth utilization, High Memory Bandwidth (HMB), Memory access slowdown, Memory interference, Memory-centric scheduling}
}
Document
Invited Paper
DOI: 10.4230/OASIcs.NG-RES.2024.2
A Multi-Modal Distributed Real-Time IoT System for Urban Traffic Control (Invited Paper)

Authors: Zeba Khanam, Vejey Pradeep Suresh Achari, Issam Boukhennoufa, Anish Jindal, and Amit Kumar Singh

Published in: OASIcs, Volume 117, Fifth Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2024)

Abstract
Traffic congestion is one of the growing urban problem with associated problems like fuel wastage, loss of lives, and slow productivity. The existing traffic system uses programming logic control (PLC) with round-robin scheduling algorithm. Recent works have proposed IoT-based frameworks that use traffic density of each lane to control traffic movement, but they suffer from low accuracy due to lack of emergency vehicle image datasets for training deep neural networks. In this paper, we propose a novel distributed IoT framework that is based on two observations. The first observation is major structural changes to road are rare. This observation is exploited by proposing a novel two stage vehicle detector that is able to achieve 77% vehicle detection accuracy on UA-DETRAC dataset. The second observation is emergency vehicle have distinct siren sound that is detected using a novel acoustic detection algorithm on an edge device. The proposed system is able to detect emergency vehicles with an average accuracy of 99.4%.
Cite as

Zeba Khanam, Vejey Pradeep Suresh Achari, Issam Boukhennoufa, Anish Jindal, and Amit Kumar Singh. A Multi-Modal Distributed Real-Time IoT System for Urban Traffic Control (Invited Paper). In Fifth Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2024). Open Access Series in Informatics (OASIcs), Volume 117, pp. 2:1-2:10, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2024)

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@InProceedings{khanam_et_al:OASIcs.NG-RES.2024.2,
  author =	{Khanam, Zeba and Achari, Vejey Pradeep Suresh and Boukhennoufa, Issam and Jindal, Anish and Singh, Amit Kumar},
  title =	{{A Multi-Modal Distributed Real-Time IoT System for Urban Traffic Control}},
  booktitle =	{Fifth Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2024)},
  pages =	{2:1--2:10},
  series =	{Open Access Series in Informatics (OASIcs)},
  ISBN =	{978-3-95977-313-3},
  ISSN =	{2190-6807},
  year =	{2024},
  volume =	{117},
  editor =	{Yomsi, Patrick Meumeu and Wildermann, Stefan},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops-dev.dagstuhl.de/entities/document/10.4230/OASIcs.NG-RES.2024.2},
  URN =		{urn:nbn:de:0030-drops-197057},
  doi =		{10.4230/OASIcs.NG-RES.2024.2},
  annote =	{Keywords: Vehicle Detection, Deep Neural Network, Traffic Control, Edge Computing, Emergency Vehicle Detection, Sliding Window}
}
Document
Invited Paper
DOI: 10.4230/OASIcs.NG-RES.2024.3
DynaVLC - Towards Dynamic GTS Allocation in VLC Networks (Invited Paper)

Authors: Harrison Kurunathan, Miguel Gutiérrez Gaitán, Ramiro Sámano-Robles, and Eduardo Tovar

Published in: OASIcs, Volume 117, Fifth Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2024)

Abstract
Envisioned to deliver superior Quality of Service (QoS) by offering faster data rates and reduced latency in 6G communication scenarios, pioneering communication protocols like the IEEE 802.15.7 are poised to facilitate emerging application trends (e.g. metaverse). The IEEE 802.15.7 standard that supports visible light communication (VLC) provides determinism for time-critical reliable communication through its guaranteed time-slots mechanism of the contention-free period (CFP) while supporting non-time-critical communication through contention-access period (CAP). Nevertheless, the IEEE 802.15.7 MAC structure is fixed and statically defined at the beginning of the network creation. This rigid definition of the network can be detrimental when the traffic characteristics evolve dynamically, for example, due to environmental or user-driven workload conditions. To this purpose, this paper proposes a resource-aware dynamic architecture for IEEE 802.15.7 networks that efficiently adapts the superframe structure to traffic dynamics. Notably, this technique was shown to reduce the overall delay and throughput by up to 45% and 30%, respectively, when compared to the traditional IEEE 802.15.7 protocol performance under the same network conditions.
Cite as

Harrison Kurunathan, Miguel Gutiérrez Gaitán, Ramiro Sámano-Robles, and Eduardo Tovar. DynaVLC - Towards Dynamic GTS Allocation in VLC Networks (Invited Paper). In Fifth Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2024). Open Access Series in Informatics (OASIcs), Volume 117, pp. 3:1-3:11, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2024)

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@InProceedings{kurunathan_et_al:OASIcs.NG-RES.2024.3,
  author =	{Kurunathan, Harrison and Gait\'{a}n, Miguel Guti\'{e}rrez and S\'{a}mano-Robles, Ramiro and Tovar, Eduardo},
  title =	{{DynaVLC - Towards Dynamic GTS Allocation in VLC Networks}},
  booktitle =	{Fifth Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2024)},
  pages =	{3:1--3:11},
  series =	{Open Access Series in Informatics (OASIcs)},
  ISBN =	{978-3-95977-313-3},
  ISSN =	{2190-6807},
  year =	{2024},
  volume =	{117},
  editor =	{Yomsi, Patrick Meumeu and Wildermann, Stefan},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops-dev.dagstuhl.de/entities/document/10.4230/OASIcs.NG-RES.2024.3},
  URN =		{urn:nbn:de:0030-drops-197069},
  doi =		{10.4230/OASIcs.NG-RES.2024.3},
  annote =	{Keywords: IEEE 802.15.7, VLC networks, network tuning}
}
Document
DOI: 10.4230/OASIcs.NG-RES.2024.4
History-Based Run-Time Requirement Enforcement of Non-Functional Properties on MPSoCs

Authors: Khalil Esper and Jürgen Teich

Published in: OASIcs, Volume 117, Fifth Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2024)

Abstract
Embedded system applications usually have requirements regarding non-functional properties of their execution like latency or power consumption. Enforcement of such requirements can be implemented by a reactive control loop, where an enforcer determines based on a system response (feedback) how to control the system, e.g., by selecting the number of active cores allocated to a program or by scaling their voltage/frequency mode. It is of a particular interest to design enforcement strategies for which it is possible to provide formal guarantees with respect to requirement violations, especially under a largely varying environmental input (workload) per execution. In this paper, we consider enforcement strategies that are modeled by a finite state machine (FSM) and the environment by a discrete-time Markov chain. Such a formalization enables the formal verification of temporal properties (verification goals) regarding the satisfaction of requirements of a given enforcement strategy. In this paper, we propose history-based enforcement FSMs which compute a reaction not just on the current, but on a fixed history of K previously observed system responses. We then analyze the quality of such enforcement FSMs in terms of the probability of satisfying a given set of verification goals and compare them to enforcement FSMs that react solely on the current system response. As experimental results, we present three use cases while considering requirements on latency and power consumption. The results show that history-based enforcement FSMs outperform enforcement FSMs that only consider the current system response regarding the probability of satisfying a given set of verification goals.
Cite as

Khalil Esper and Jürgen Teich. History-Based Run-Time Requirement Enforcement of Non-Functional Properties on MPSoCs. In Fifth Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2024). Open Access Series in Informatics (OASIcs), Volume 117, pp. 4:1-4:11, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2024)

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@InProceedings{esper_et_al:OASIcs.NG-RES.2024.4,
  author =	{Esper, Khalil and Teich, J\"{u}rgen},
  title =	{{History-Based Run-Time Requirement Enforcement of Non-Functional Properties on MPSoCs}},
  booktitle =	{Fifth Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2024)},
  pages =	{4:1--4:11},
  series =	{Open Access Series in Informatics (OASIcs)},
  ISBN =	{978-3-95977-313-3},
  ISSN =	{2190-6807},
  year =	{2024},
  volume =	{117},
  editor =	{Yomsi, Patrick Meumeu and Wildermann, Stefan},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops-dev.dagstuhl.de/entities/document/10.4230/OASIcs.NG-RES.2024.4},
  URN =		{urn:nbn:de:0030-drops-197074},
  doi =		{10.4230/OASIcs.NG-RES.2024.4},
  annote =	{Keywords: Verification, Runtime Requirement Enforcement, History, Latency}
}
Document
DOI: 10.4230/OASIcs.NG-RES.2021.2
EDF Scheduling and Minimal-Overlap Shortest-Path Routing for Real-Time TSCH Networks

Authors: Miguel Gutiérrez Gaitán, Luís Almeida, Pedro Miguel Santos, and Patrick Meumeu Yomsi

Published in: OASIcs, Volume 87, Second Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2021)

Abstract
With the scope of Industry 4.0 and the Industrial Internet of Things (IIoT), wireless technologies have gained momentum in the industrial realm. Wireless standards such as WirelessHART, ISA100.11a, IEEE 802.15.4e and 6TiSCH are among the most popular, given their suitability to support real-time data traffic in wireless sensor and actuator networks (WSAN). Theoretical and empirical studies have covered prioritized packet scheduling in extenso, but only little has been done concerning methods that enhance and/or guarantee real-time performance based on routing decisions. In this work, we propose a greedy heuristic to reduce overlap in shortest-path routing for WSANs with packet transmissions scheduled under the earliest-deadline-first (EDF) policy. We evaluated our approach under varying network configurations and observed remarkable dominance in terms of the number of overlaps, transmission conflicts, and schedulability, regardless of the network workload and connectivity. We further observe that well-known graph network parameters, e.g., vertex degree, density, betweenness centrality, etc., have a special influence on the path overlaps, and thus provide useful insights to improve the real-time performance of the network.
Cite as

Miguel Gutiérrez Gaitán, Luís Almeida, Pedro Miguel Santos, and Patrick Meumeu Yomsi. EDF Scheduling and Minimal-Overlap Shortest-Path Routing for Real-Time TSCH Networks. In Second Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2021). Open Access Series in Informatics (OASIcs), Volume 87, pp. 2:1-2:12, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2021)

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@InProceedings{gaitan_et_al:OASIcs.NG-RES.2021.2,
  author =	{Gait\'{a}n, Miguel Guti\'{e}rrez and Almeida, Lu{\'\i}s and Santos, Pedro Miguel and Yomsi, Patrick Meumeu},
  title =	{{EDF Scheduling and Minimal-Overlap Shortest-Path Routing for Real-Time TSCH Networks}},
  booktitle =	{Second Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2021)},
  pages =	{2:1--2:12},
  series =	{Open Access Series in Informatics (OASIcs)},
  ISBN =	{978-3-95977-178-8},
  ISSN =	{2190-6807},
  year =	{2021},
  volume =	{87},
  editor =	{Bertogna, Marko and Terraneo, Federico},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops-dev.dagstuhl.de/entities/document/10.4230/OASIcs.NG-RES.2021.2},
  URN =		{urn:nbn:de:0030-drops-134786},
  doi =		{10.4230/OASIcs.NG-RES.2021.2},
  annote =	{Keywords: Real-time communication, Routing, Scheduling, TDMA, Wireless networks}
}
Document
DOI: 10.4230/OASIcs.WCET.2017.10
The P-SOCRATES Timing Analysis Methodology for Parallel Real-Time Applications Deployed on Many-Core Platforms

Authors: Vincent Nelis, Patrick Meumeu Yomsi, and Luís Miguel Pinho

Published in: OASIcs, Volume 57, 17th International Workshop on Worst-Case Execution Time Analysis (WCET 2017)

Abstract
This paper presents the timing analysis methodology developed in the European project P-SOCRATES (Parallel Software Framework for Time-Critical Many-core Systems). This timing analysis methodology is defined for parallel applications that must satisfy both performance and real-time requirements and are executed on modern many-core processor architectures. We discuss the motivation and objectives of the project, the timing analysis flow that we proposed, the tool that has been developed to automatize it, and finally we report on some of the preliminary results that we have obtained when applying this methodology to the three application use-cases of the project.
Cite as

Vincent Nelis, Patrick Meumeu Yomsi, and Luís Miguel Pinho. The P-SOCRATES Timing Analysis Methodology for Parallel Real-Time Applications Deployed on Many-Core Platforms. In 17th International Workshop on Worst-Case Execution Time Analysis (WCET 2017). Open Access Series in Informatics (OASIcs), Volume 57, pp. 10:1-10:9, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2017)

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@InProceedings{nelis_et_al:OASIcs.WCET.2017.10,
  author =	{Nelis, Vincent and Yomsi, Patrick Meumeu and Pinho, Lu{\'\i}s Miguel},
  title =	{{The P-SOCRATES Timing Analysis Methodology for Parallel Real-Time Applications Deployed on Many-Core Platforms}},
  booktitle =	{17th International Workshop on Worst-Case Execution Time Analysis (WCET 2017)},
  pages =	{10:1--10:9},
  series =	{Open Access Series in Informatics (OASIcs)},
  ISBN =	{978-3-95977-057-6},
  ISSN =	{2190-6807},
  year =	{2017},
  volume =	{57},
  editor =	{Reineke, Jan},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops-dev.dagstuhl.de/entities/document/10.4230/OASIcs.WCET.2017.10},
  URN =		{urn:nbn:de:0030-drops-73120},
  doi =		{10.4230/OASIcs.WCET.2017.10},
  annote =	{Keywords: Timing analysis, many-core platform}
}
Document
DOI: 10.4230/OASIcs.WCET.2016.6
The Variability of Application Execution Times on a Multi-Core Platform

Authors: Vincent Nélis, Patrick Meumeu Yomsi, and Luís Miguel Pinho

Published in: OASIcs, Volume 55, 16th International Workshop on Worst-Case Execution Time Analysis (WCET 2016)

Abstract
It is a known fact that processes running concurrently on different cores in a multicore environment interfere with each other on the processor shared resources. The contention on these shared resources considerably slows down the execution on every core since sometimes the cores must stall while their requests to access the resources are being served. But by how much the execution may be slowed down due to this interference? In this paper we answer this question with numbers coming from experimentation. That is, we quantify the magnitude of the impact of the interference on the execution time by running programs taken from the TACLeBench benchmark suite, a popular benchmark suite in the real-time research community, on the first generation of Kalray manycore processor family, the MPPA-256 (the development board) that goes by the codename "Andey".
Cite as

Vincent Nélis, Patrick Meumeu Yomsi, and Luís Miguel Pinho. The Variability of Application Execution Times on a Multi-Core Platform. In 16th International Workshop on Worst-Case Execution Time Analysis (WCET 2016). Open Access Series in Informatics (OASIcs), Volume 55, pp. 6:1-6:11, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2016)

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@InProceedings{nelis_et_al:OASIcs.WCET.2016.6,
  author =	{N\'{e}lis, Vincent and Yomsi, Patrick Meumeu and Pinho, Lu{\'\i}s Miguel},
  title =	{{The Variability of Application Execution Times on a Multi-Core Platform}},
  booktitle =	{16th International Workshop on Worst-Case Execution Time Analysis (WCET 2016)},
  pages =	{6:1--6:11},
  series =	{Open Access Series in Informatics (OASIcs)},
  ISBN =	{978-3-95977-025-5},
  ISSN =	{2190-6807},
  year =	{2016},
  volume =	{55},
  editor =	{Schoeberl, Martin},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.WCET.2016.6},
  URN =		{urn:nbn:de:0030-drops-68994},
  doi =		{10.4230/OASIcs.WCET.2016.6},
  annote =	{Keywords: Execution time variability, timing analysis, WCET estimates, multi-cores, many-cores}
}
Document
DOI: 10.4230/OASIcs.WCET.2014.63
The Challenge of Time-Predictability in Modern Many-Core Architectures

Authors: Vincent Nélis, Patrick Meumeu Yomsi, Luís Miguel Pinho, José Carlos Fonseca, Marko Bertogna, Eduardo Quiñones, Roberto Vargas, and Andrea Marongiu

Published in: OASIcs, Volume 39, 14th International Workshop on Worst-Case Execution Time Analysis (2014)

Abstract
The recent technological advancements and market trends are causing an interesting phenomenon towards the convergence of High-Performance Computing (HPC) and Embedded Computing (EC) domains. Many recent HPC applications require huge amounts of information to be processed within a bounded amount of time while EC systems are increasingly concerned with providing higher performance in real-time. The convergence of these two domains towards systems requiring both high performance and a predictable time-behavior challenges the capabilities of current hardware architectures. Fortunately, the advent of next-generation many-core embedded platforms has the chance of intercepting this converging need for predictability and high-performance, allowing HPC and EC applications to be executed on efficient and powerful heterogeneous architectures integrating general-purpose processors with many-core computing fabrics. However, addressing this mixed set of requirements is not without its own challenges and it is now of paramount importance to develop new techniques to exploit the massively parallel computation capabilities of many-core platforms in a predictable way.
Cite as

Vincent Nélis, Patrick Meumeu Yomsi, Luís Miguel Pinho, José Carlos Fonseca, Marko Bertogna, Eduardo Quiñones, Roberto Vargas, and Andrea Marongiu. The Challenge of Time-Predictability in Modern Many-Core Architectures. In 14th International Workshop on Worst-Case Execution Time Analysis. Open Access Series in Informatics (OASIcs), Volume 39, pp. 63-72, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2014)

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@InProceedings{nelis_et_al:OASIcs.WCET.2014.63,
  author =	{N\'{e}lis, Vincent and Yomsi, Patrick Meumeu and Pinho, Lu{\'\i}s Miguel and Fonseca, Jos\'{e} Carlos and Bertogna, Marko and Qui\~{n}ones, Eduardo and Vargas, Roberto and Marongiu, Andrea},
  title =	{{The Challenge of Time-Predictability in Modern Many-Core Architectures}},
  booktitle =	{14th International Workshop on Worst-Case Execution Time Analysis},
  pages =	{63--72},
  series =	{Open Access Series in Informatics (OASIcs)},
  ISBN =	{978-3-939897-69-9},
  ISSN =	{2190-6807},
  year =	{2014},
  volume =	{39},
  editor =	{Falk, Heiko},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.WCET.2014.63},
  URN =		{urn:nbn:de:0030-drops-46050},
  doi =		{10.4230/OASIcs.WCET.2014.63},
  annote =	{Keywords: Time-Predictability, Many-Cores, Multi-Cores, Timing Analysis}
}
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