Volume

Dagstuhl Seminar Proceedings, Volume 10281

Publication Details

  • published at: 2010-12-14
  • Publisher: Schloss Dagstuhl – Leibniz-Zentrum für Informatik

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Document
DOI: 10.4230/DagSemProc.10281.1
10281 Abstracts Collection – Dynamically Reconfigurable Architectures

Authors: Peter M. Athanas, Jürgen Becker, Jürgen Teich, and Ingrid Verbauwhede

Abstract
From 11.07.10 to 16.07.10, Dagstuhl Seminar 10281 ``Dynamically Reconfigurable Architectures '' was held in Schloss Dagstuhl~--~Leibniz Center for Informatics. During the seminar, several participants presented their current research, and ongoing work and open problems were discussed. Abstracts of the presentations given during the seminar as well as abstracts of seminar results and ideas are put together in this paper. The first section describes the seminar topics and goals in general. Links to extended abstracts or full papers are provided, if available.
Cite as

Peter M. Athanas, Jürgen Becker, Jürgen Teich, and Ingrid Verbauwhede. 10281 Abstracts Collection – Dynamically Reconfigurable Architectures. In Dynamically Reconfigurable Architectures. Dagstuhl Seminar Proceedings, Volume 10281, pp. 1-23, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2010)

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@InProceedings{athanas_et_al:DagSemProc.10281.1,
  author =	{Athanas, Peter M. and Becker, J\"{u}rgen and Teich, J\"{u}rgen and Verbauwhede, Ingrid},
  title =	{{10281 Abstracts Collection – Dynamically Reconfigurable Architectures}},
  booktitle =	{Dynamically Reconfigurable Architectures},
  pages =	{1--23},
  series =	{Dagstuhl Seminar Proceedings (DagSemProc)},
  ISSN =	{1862-4405},
  year =	{2010},
  volume =	{10281},
  editor =	{Peter M. Athanas and J\"{u}rgen Becker and J\"{u}rgen Teich and Ingrid Verbauwhede},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/DagSemProc.10281.1},
  URN =		{urn:nbn:de:0030-drops-28962},
  doi =		{10.4230/DagSemProc.10281.1},
  annote =	{Keywords: Dynamically Run-Time Reconfigurable Computing Architectures, Self- adaptive Systems, Computational Models, Circuit Technologies, System Architecture, Reconfigurable/Adaptive Computing based on Nanotechnologies}
}
Document
DOI: 10.4230/DagSemProc.10281.2
10281 Summary – Dynamically Reconfigurable Architectures

Authors: Peter M. Athanas, Jürgen Becker, Jürgen Teich, and Ingrid Verbauwhede

Abstract
Dynamic and partial reconfiguration of hardware architectures such as FPGAs and coarse grain processing arrays bring an additional level of flexibility in the design of electronic systems by exploiting the possibility of configuring functions on-demand during run-time. When compared to emerging software-programmable Multi-Processor System-on-a-Chip (MPSoC) solutions, they benefit a lot from lower cost, more dedication and fit to a certain problem class as well as power and area efficiency. This has led to many new ways of approaching existing research topics in the area of hardware design and optimization techniques. For example, the possibility of performing adaptation during run-time raises questions in the areas of dynamic control, real-time response, on-line power management and design complexity, since the reconfigurability increases the design space towards infinity.
Cite as

Peter M. Athanas, Jürgen Becker, Jürgen Teich, and Ingrid Verbauwhede. 10281 Summary – Dynamically Reconfigurable Architectures. In Dynamically Reconfigurable Architectures. Dagstuhl Seminar Proceedings, Volume 10281, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2010)

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@InProceedings{athanas_et_al:DagSemProc.10281.2,
  author =	{Athanas, Peter M. and Becker, J\"{u}rgen and Teich, J\"{u}rgen and Verbauwhede, Ingrid},
  title =	{{10281 Summary – Dynamically Reconfigurable Architectures}},
  booktitle =	{Dynamically Reconfigurable Architectures},
  series =	{Dagstuhl Seminar Proceedings (DagSemProc)},
  ISSN =	{1862-4405},
  year =	{2010},
  volume =	{10281},
  editor =	{Peter M. Athanas and J\"{u}rgen Becker and J\"{u}rgen Teich and Ingrid Verbauwhede},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/DagSemProc.10281.2},
  URN =		{urn:nbn:de:0030-drops-28926},
  doi =		{10.4230/DagSemProc.10281.2},
  annote =	{Keywords: Dynamically Run-Time Reconfigurable Computing Architectures, Self- adaptive Systems, Computational Models, Circuit Technologies, System Architecture, CAD Tool Support, Reconfigurable/Adaptive Computing based on Nanotechnologies}
}
Document
DOI: 10.4230/DagSemProc.10281.3
A mathematical approach towards hardware design

Authors: Gerard J. M. Smit, Jan Kuper, and Christiaan P. R. Baaij

Abstract
Today the hardware for embedded systems is often specified in VHDL. However, VHDL describes the system at a rather low level, which is cumbersome and may lead to design faults in large real life applications. There is a need of higher level abstraction mechanisms. In the embedded systems group of the University of Twente we are working on systematic and transformational methods to design hardware architectures, both multi core and single core. The main line in this approach is to start with a straightforward (often mathematical) specification of the problem. The next step is to find some adequate transformations on this specification, in particular to find specific optimizations, to be able to distribute the application over different cores. The result of these transformations is then translated into the functional programming language Haskell since Haskell is close to mathematics and such a translation often is straightforward. Besides, the Haskell code is executable, so one immediately has a simulation of the intended system. Next, the resulting Haskell specification is given to a compiler, called CëaSH (for CAES LAnguage for Synchronous Hardware) which translates the specification into VHDL. The resulting VHDL is synthesizable, so from there on standard VHDL-tooling can be used for synthesis. In this work we primarily focus on streaming applications: i.e. applications that can be modeled as data-flow graphs. At the moment the CëaSH system is ready in prototype form and in the presentation we will give several examples of how it can be used. In these examples it will be shown that the specification code is clear and concise. Furthermore, it is possible to use powerful abstraction mechanisms, such as polymorphism, higher order functions, pattern matching, lambda abstraction, partial application. These features allow a designer to describe circuits in a more natural and concise way than possible with the language elements found in the traditional hardware description languages. In addition we will give some examples of transformations that are possible in a mathematical specification, and which do not suffer from the problems encountered in, e.g., automatic parallelization of nested for-loops in C-programs.
Cite as

Gerard J. M. Smit, Jan Kuper, and Christiaan P. R. Baaij. A mathematical approach towards hardware design. In Dynamically Reconfigurable Architectures. Dagstuhl Seminar Proceedings, Volume 10281, pp. 1-11, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2010)

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@InProceedings{smit_et_al:DagSemProc.10281.3,
  author =	{Smit, Gerard J. M. and Kuper, Jan and Baaij, Christiaan P. R.},
  title =	{{A mathematical approach towards hardware design}},
  booktitle =	{Dynamically Reconfigurable Architectures},
  pages =	{1--11},
  series =	{Dagstuhl Seminar Proceedings (DagSemProc)},
  ISSN =	{1862-4405},
  year =	{2010},
  volume =	{10281},
  editor =	{Peter M. Athanas and J\"{u}rgen Becker and J\"{u}rgen Teich and Ingrid Verbauwhede},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/DagSemProc.10281.3},
  URN =		{urn:nbn:de:0030-drops-28407},
  doi =		{10.4230/DagSemProc.10281.3},
  annote =	{Keywords: Hardware design, mathematical specification, streaming applications}
}
Document
DOI: 10.4230/DagSemProc.10281.4
A new project to address run-time reconfigurable hardware systems

Authors: Jim Torresen and Dirk Koch

Abstract
Last autumn, we started a new project named Context Switching Reconfigurable Hardware for Communication Systems (COSRECOS). In this talk, I would like to present how we plan to address the challenge of changing hardware configurations while a system is in operation. The overall goal of the project is to contribute in making run-time reconfigurable systems more feasible in general. This includes introducing architectures for reducing reconfiguration time as well as undertaking tool development. Case studies by applications in network and communication systems will be a part of the project. Comments to the planned outline are much welcome.
Cite as

Jim Torresen and Dirk Koch. A new project to address run-time reconfigurable hardware systems. In Dynamically Reconfigurable Architectures. Dagstuhl Seminar Proceedings, Volume 10281, pp. 1-10, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2010)

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@InProceedings{torresen_et_al:DagSemProc.10281.4,
  author =	{Torresen, Jim and Koch, Dirk},
  title =	{{A new project to address run-time reconfigurable hardware systems}},
  booktitle =	{Dynamically Reconfigurable Architectures},
  pages =	{1--10},
  series =	{Dagstuhl Seminar Proceedings (DagSemProc)},
  ISSN =	{1862-4405},
  year =	{2010},
  volume =	{10281},
  editor =	{Peter M. Athanas and J\"{u}rgen Becker and J\"{u}rgen Teich and Ingrid Verbauwhede},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/DagSemProc.10281.4},
  URN =		{urn:nbn:de:0030-drops-28943},
  doi =		{10.4230/DagSemProc.10281.4},
  annote =	{Keywords: }
}
Document
DOI: 10.4230/DagSemProc.10281.5
Advances in Component-based System Design and Partial Run-time Reconfiguration

Authors: Dirk Koch

Abstract
With passing over the 1M LUT barrier, FPGA technology is heading into new challenges and opportunities. While the present ASIC-like design methodology and tools will struggle to scale with such huge devices, providing partial run-time reconfiguration will be become obligatory for dealing with long configuration times and the increasing vulnerability to single event upsets. Within the COSRECOS project, we address these issues by developing methods and tools that allow to compose systems rapidly by plugging together fully physically implemented components. Moreover, by allowing a hot-swapping of such components, the tremendous advantages of partial run-time reconfiguration can be utilized. This talk will give an overview of recent trends, our present research activities, and will discuss open issues.
Cite as

Dirk Koch. Advances in Component-based System Design and Partial Run-time Reconfiguration. In Dynamically Reconfigurable Architectures. Dagstuhl Seminar Proceedings, Volume 10281, pp. 1-9, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2010)

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@InProceedings{koch:DagSemProc.10281.5,
  author =	{Koch, Dirk},
  title =	{{Advances in Component-based System Design and Partial Run-time Reconfiguration}},
  booktitle =	{Dynamically Reconfigurable Architectures},
  pages =	{1--9},
  series =	{Dagstuhl Seminar Proceedings (DagSemProc)},
  ISSN =	{1862-4405},
  year =	{2010},
  volume =	{10281},
  editor =	{Peter M. Athanas and J\"{u}rgen Becker and J\"{u}rgen Teich and Ingrid Verbauwhede},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/DagSemProc.10281.5},
  URN =		{urn:nbn:de:0030-drops-28410},
  doi =		{10.4230/DagSemProc.10281.5},
  annote =	{Keywords: FPGA design, partial reconfiguretion, component-based design}
}
Document
DOI: 10.4230/DagSemProc.10281.6
Compiling Geometric Algebra Computations into Reconfigurable Hardware Accelerators

Authors: Jens Huthmann, Peter Müller, Florian Stock, Dietmar Hildenbrand, and Andreas Koch

Abstract
Geometric Algebra (GA), a generalization of quaternions and complex numbers, is a very powerful framework for intuitively expressing and manipulating the complex geometric relationships common to engineering problems. However, actual processing of GA expressions is very compute intensive, and acceleration is generally required for practical use. GPUs and FPGAs offer such acceleration, while requiring only low-power per operation. In this paper, we present key components of a proof-of-concept compile flow combining symbolic and hardware optimization techniques to automatically generate hardware accelerators from the abstract GA descriptions that are suitable for high-performance embedded computing.
Cite as

Jens Huthmann, Peter Müller, Florian Stock, Dietmar Hildenbrand, and Andreas Koch. Compiling Geometric Algebra Computations into Reconfigurable Hardware Accelerators. In Dynamically Reconfigurable Architectures. Dagstuhl Seminar Proceedings, Volume 10281, pp. 1-15, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2010)

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@InProceedings{huthmann_et_al:DagSemProc.10281.6,
  author =	{Huthmann, Jens and M\"{u}ller, Peter and Stock, Florian and Hildenbrand, Dietmar and Koch, Andreas},
  title =	{{Compiling Geometric Algebra Computations into Reconfigurable  Hardware Accelerators}},
  booktitle =	{Dynamically Reconfigurable Architectures},
  pages =	{1--15},
  series =	{Dagstuhl Seminar Proceedings (DagSemProc)},
  ISSN =	{1862-4405},
  year =	{2010},
  volume =	{10281},
  editor =	{Peter M. Athanas and J\"{u}rgen Becker and J\"{u}rgen Teich and Ingrid Verbauwhede},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/DagSemProc.10281.6},
  URN =		{urn:nbn:de:0030-drops-28389},
  doi =		{10.4230/DagSemProc.10281.6},
  annote =	{Keywords: Geometric Algebra FPGA High-Level-Compiler Gaalop}
}
Document
DOI: 10.4230/DagSemProc.10281.7
Design and Implementation of an Object-Oriented DPR-Framework

Authors: Norbert Abel

Abstract
Nowadays, two innovative future trends regarding hardware development and hardware description can be found. The first trend concerns the hardware itself. Modern Xilinx FPGAs provide the possibility to be reconfigured partially and dynamically - which is called dynamical partial reconfiguration (DPR). DPR opens a huge field of new functionalities on FPGAs. However, using DPR means struggling with architectural details of the used FPGAs and the according synthesis and implementation tools. A developer would focus most of the time on DPR and only a small part of the time on the implementation of the actual modules - of course that is the opposite of what hardware engineers want to do. The second trend concerns the way hardware is described. Many hardware developing groups are looking forward to an HDL which operates on the algorithmic level, since this would come with a significant increase in productivity. The aim is to be able to translate common software algorithms to hardware in an efficient way (which is called high-level synthesis or HLS). Although both DPR and HLS are important future trends regarding hardware design, they develop quite independently. Today's software-to-hardware compilers focus on conventional hardware and therefore have to remove dynamic aspects such as the instantiation of calculating modules at runtime. Even object-oriented languages like SystemC do not support the dynamic instantiation of objects (that means the usage of new or delete outside of the constructor) for synthesis at all. On the other hand, DPR tools are working on the lowest possible layer regarding FPGAs: the bitfile level. Our research focuses on the design and the implementation of a Framework combining the two technologies, since this has the potential to kill two birds with one stone. Firstly, DPR can change the programming paradigm in future HDLs regarding dynamic instantiations. Dynamic parts would not have to be removed any longer but could be realized on the target FPGA using DPR. Secondly, a high-level language support of DPR technologies could help end its shadowy existence and turn it into a commonly used method.
Cite as

Norbert Abel. Design and Implementation of an Object-Oriented DPR-Framework. In Dynamically Reconfigurable Architectures. Dagstuhl Seminar Proceedings, Volume 10281, pp. 1-9, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2010)

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@InProceedings{abel:DagSemProc.10281.7,
  author =	{Abel, Norbert},
  title =	{{Design and Implementation of an Object-Oriented DPR-Framework}},
  booktitle =	{Dynamically Reconfigurable Architectures},
  pages =	{1--9},
  series =	{Dagstuhl Seminar Proceedings (DagSemProc)},
  ISSN =	{1862-4405},
  year =	{2010},
  volume =	{10281},
  editor =	{Peter M. Athanas and J\"{u}rgen Becker and J\"{u}rgen Teich and Ingrid Verbauwhede},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/DagSemProc.10281.7},
  URN =		{urn:nbn:de:0030-drops-28365},
  doi =		{10.4230/DagSemProc.10281.7},
  annote =	{Keywords: FPGA, DPR, HLS, Object-Orientation}
}
Document
DOI: 10.4230/DagSemProc.10281.8
Lessons Learned from last 4 Years of Reconfigurable Computing

Authors: Walter Stechele, Christopher Claus, and Andreas Laika

Abstract
Partial dynamic reconfiguration of FPGAs was investigated for video-based driver assistance applications during the last 4 years. High-level application software was combined with dynamically reconfigurable hardware accelerators in selected scenarios, e.g. vehicle lights detection, optical flow motion detection. From the beginning of the project, various research challenges have been targeted, including hardware/software partitioning between embedded RISC and accelerators, granularity of reconfigurable regions, as well as the impact of the reconfiguration process on system performance. This article will review the status of these research challenges and present an outlook on future challenges, including reconfiguration look ahead. Challenges will be illustrated on robotic vision scenarios with dynamically changing computational load from soft real-time and hard real-time applications.
Cite as

Walter Stechele, Christopher Claus, and Andreas Laika. Lessons Learned from last 4 Years of Reconfigurable Computing. In Dynamically Reconfigurable Architectures. Dagstuhl Seminar Proceedings, Volume 10281, pp. 1-7, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2010)

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@InProceedings{stechele_et_al:DagSemProc.10281.8,
  author =	{Stechele, Walter and Claus, Christopher and Laika, Andreas},
  title =	{{Lessons Learned from last 4 Years of Reconfigurable Computing}},
  booktitle =	{Dynamically Reconfigurable Architectures},
  pages =	{1--7},
  series =	{Dagstuhl Seminar Proceedings (DagSemProc)},
  ISSN =	{1862-4405},
  year =	{2010},
  volume =	{10281},
  editor =	{Peter M. Athanas and J\"{u}rgen Becker and J\"{u}rgen Teich and Ingrid Verbauwhede},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/DagSemProc.10281.8},
  URN =		{urn:nbn:de:0030-drops-28352},
  doi =		{10.4230/DagSemProc.10281.8},
  annote =	{Keywords: Reconfigurable computing, vision-based driver assistance}
}
Document
DOI: 10.4230/DagSemProc.10281.9
Low-Power Reconfigurable Architectures for High-Performance Mobile Nodes

Authors: Matthias Hanke, Tim Kranich, Mladen Berekovic, and Yannis Papaefstathiou

Abstract
Modern embedded systems have an emerging demand on high performance and low power circuits. Traditionally special functional units for each application are developed separately. These are plugged to a general purpose processors to extend its instruction set making it an application specific instruction set processor. As this strategy reaches its boundaries in area and complexity reconfigurable architectures propose to be more flexible. Thus combining both approaches to a reconfigurable application specific processor is going to be the upcoming solution for future embedded systems.
Cite as

Matthias Hanke, Tim Kranich, Mladen Berekovic, and Yannis Papaefstathiou. Low-Power Reconfigurable Architectures for High-Performance Mobile Nodes. In Dynamically Reconfigurable Architectures. Dagstuhl Seminar Proceedings, Volume 10281, pp. 1-7, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2010)

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@InProceedings{hanke_et_al:DagSemProc.10281.9,
  author =	{Hanke, Matthias and Kranich, Tim and Berekovic, Mladen and Papaefstathiou, Yannis},
  title =	{{Low-Power Reconfigurable Architectures for High-Performance Mobile Nodes}},
  booktitle =	{Dynamically Reconfigurable Architectures},
  pages =	{1--7},
  series =	{Dagstuhl Seminar Proceedings (DagSemProc)},
  ISSN =	{1862-4405},
  year =	{2010},
  volume =	{10281},
  editor =	{Peter M. Athanas and J\"{u}rgen Becker and J\"{u}rgen Teich and Ingrid Verbauwhede},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/DagSemProc.10281.9},
  URN =		{urn:nbn:de:0030-drops-28370},
  doi =		{10.4230/DagSemProc.10281.9},
  annote =	{Keywords: Reconfiguration, ASIP, RASIP, low power, high performance, video encoding, encryption, wireless sensor node, mobile device}
}
Document
DOI: 10.4230/DagSemProc.10281.10
New Directions for IP Core Watermarking and Identification

Authors: Daniel Ziener and Jürgen Teich

Abstract
In this talk, we present watermarking and identification techniques for FPGA IP cores. Unlike most existing watermarking techniques, the focus of our techniques lies on ease of verification, even if the protected cores are embedded into a product. Moreover, we have concentrated on higher abstraction levels for embedding the watermark, particularly at the logic level, where IP cores are distributed as netlist cores. With the presented watermarking methods, it is possible to watermark IP cores at the logic level and identify them with a high likelihood and in a reproducible way in a purchased product from a company that is suspected to have committed IP fraud. The investigated techniques establish the authorship by verification of either an FPGA bitfile or the power consumption of a given FPGA.
Cite as

Daniel Ziener and Jürgen Teich. New Directions for IP Core Watermarking and Identification. In Dynamically Reconfigurable Architectures. Dagstuhl Seminar Proceedings, Volume 10281, pp. 1-13, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2010)

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@InProceedings{ziener_et_al:DagSemProc.10281.10,
  author =	{Ziener, Daniel and Teich, J\"{u}rgen},
  title =	{{New Directions for IP Core Watermarking and Identification}},
  booktitle =	{Dynamically Reconfigurable Architectures},
  pages =	{1--13},
  series =	{Dagstuhl Seminar Proceedings (DagSemProc)},
  ISSN =	{1862-4405},
  year =	{2010},
  volume =	{10281},
  editor =	{Peter M. Athanas and J\"{u}rgen Becker and J\"{u}rgen Teich and Ingrid Verbauwhede},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/DagSemProc.10281.10},
  URN =		{urn:nbn:de:0030-drops-28437},
  doi =		{10.4230/DagSemProc.10281.10},
  annote =	{Keywords: IP protection, IP cores, watermarking}
}
Document
DOI: 10.4230/DagSemProc.10281.11
Secure remote reconfiguration of FPGAs

Authors: Nele Mentens, Jo Vliegen, An Braeken, Abdellah Touhafi, Karel Wouters, and Ingrid Verbauwhede

Abstract
This paper presents a solution for secure remote reconfiguration of FPGAs. Communicating the bitstream has to be done in a secure manner to prevent an attacker from reading or altering the bitstream. We propose a setup in which the FPGA is the single device in the system's zone-of-trust. The result is an FPGA architecture that is divided into a static and a dynamic region. The static region holds the communication, security and reconfiguration facilities, while the dynamic region contains the targeted application.
Cite as

Nele Mentens, Jo Vliegen, An Braeken, Abdellah Touhafi, Karel Wouters, and Ingrid Verbauwhede. Secure remote reconfiguration of FPGAs. In Dynamically Reconfigurable Architectures. Dagstuhl Seminar Proceedings, Volume 10281, pp. 1-4, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2010)

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@InProceedings{mentens_et_al:DagSemProc.10281.11,
  author =	{Mentens, Nele and Vliegen, Jo and Braeken, An and Touhafi, Abdellah and Wouters, Karel and Verbauwhede, Ingrid},
  title =	{{Secure remote reconfiguration of FPGAs}},
  booktitle =	{Dynamically Reconfigurable Architectures},
  pages =	{1--4},
  series =	{Dagstuhl Seminar Proceedings (DagSemProc)},
  ISSN =	{1862-4405},
  year =	{2010},
  volume =	{10281},
  editor =	{Peter M. Athanas and J\"{u}rgen Becker and J\"{u}rgen Teich and Ingrid Verbauwhede},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/DagSemProc.10281.11},
  URN =		{urn:nbn:de:0030-drops-28391},
  doi =		{10.4230/DagSemProc.10281.11},
  annote =	{Keywords: FPGA, cryptography, security, remote configuration}
}
Document
DOI: 10.4230/DagSemProc.10281.12
The Optimization of Interconnection Networks in FPGAs

Authors: Xiaolei Chen and Yajun Ha

Abstract
Scaling technology enables even higher degree of integration for FPGAs, but also brings new challenges that need to be addressed from both the architecture and the design tools side. Optimization of FPGA interconnection network is essential, given that interconnects dominate logic. Two approaches are presented, with one based on the time-multiplexing of wires and the other using hierarchical interconnects of high-speed serial links and switches. Design tools for both approaches are discussed. Preliminary experiments and prototypes are presented, and show positive results.
Cite as

Xiaolei Chen and Yajun Ha. The Optimization of Interconnection Networks in FPGAs. In Dynamically Reconfigurable Architectures. Dagstuhl Seminar Proceedings, Volume 10281, pp. 1-9, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2010)

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@InProceedings{chen_et_al:DagSemProc.10281.12,
  author =	{Chen, Xiaolei and Ha, Yajun},
  title =	{{The Optimization of Interconnection Networks in FPGAs}},
  booktitle =	{Dynamically Reconfigurable Architectures},
  pages =	{1--9},
  series =	{Dagstuhl Seminar Proceedings (DagSemProc)},
  ISSN =	{1862-4405},
  year =	{2010},
  volume =	{10281},
  editor =	{Peter M. Athanas and J\"{u}rgen Becker and J\"{u}rgen Teich and Ingrid Verbauwhede},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/DagSemProc.10281.12},
  URN =		{urn:nbn:de:0030-drops-28425},
  doi =		{10.4230/DagSemProc.10281.12},
  annote =	{Keywords: Field-programmable gate array, architecture, computer-aided design}
}
Document
DOI: 10.4230/DagSemProc.10281.13
Towards a reconfigurable hardware architecture for implementing a LDPC module suitable for software radio systems

Authors: Rene Cumplido, Juan Manuel Campos, Claudia Feregrino-Uribe, and Jose Roberto Perez-Andrade

Abstract
Forward Error Correction is a key piece in modern digital communications. When a signal is transmitted over a noisy channel, multiple errors are generated. FEC techniques are directed towards the recovery of such errors. In last years, LDPC (Low Density Parity Check) codes have attracted attention of researchers because of their excellent error correction capabilities, but for actual radios high performance is not enough since they require to communicate with other multiple radios too. In general, communication between multiple radios requires the use of different standards. In this sense, Software Defined Radio (SDR) approach allows building multi standard radios based on reconfigurability abilities which means that base components including recovery errors block must provide reconfigurable options. In this paper, some open problems in designing and implementing reconfigurable LDPC components are presented and discussed. Some features of works in the state of the art are commented and possible research lines proposed.
Cite as

Rene Cumplido, Juan Manuel Campos, Claudia Feregrino-Uribe, and Jose Roberto Perez-Andrade. Towards a reconfigurable hardware architecture for implementing a LDPC module suitable for software radio systems. In Dynamically Reconfigurable Architectures. Dagstuhl Seminar Proceedings, Volume 10281, pp. 1-8, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2010)

Copy BibTex To Clipboard

@InProceedings{cumplido_et_al:DagSemProc.10281.13,
  author =	{Cumplido, Rene and Campos, Juan Manuel and Feregrino-Uribe, Claudia and Perez-Andrade, Jose Roberto},
  title =	{{Towards a reconfigurable hardware architecture for implementing a LDPC module suitable for software radio systems}},
  booktitle =	{Dynamically Reconfigurable Architectures},
  pages =	{1--8},
  series =	{Dagstuhl Seminar Proceedings (DagSemProc)},
  ISSN =	{1862-4405},
  year =	{2010},
  volume =	{10281},
  editor =	{Peter M. Athanas and J\"{u}rgen Becker and J\"{u}rgen Teich and Ingrid Verbauwhede},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/DagSemProc.10281.13},
  URN =		{urn:nbn:de:0030-drops-28950},
  doi =		{10.4230/DagSemProc.10281.13},
  annote =	{Keywords: LDPC codes, Software Defined Radio, Hardware Implementation}
}
Document
DOI: 10.4230/DagSemProc.10281.14
Towards Dilated Placement of Dynamic NoC Cores

Authors: Branislav Hredzak and Oliver Diessel

Abstract
Instead of mapping application task graphs in a compact manner onto reconfigurable devices using a network-on-chip for interconnecting application cores, we propose dilating the mappings as much as the available latencies on critical connections allow. In a dilated mapping, the unused resources between an application's configured components can be used to provide additional flexibility when the configuration needs to change. We motivate the reasons for dilating application task graphs targeted at reconfigurable devices; derive a simulated annealing approach to dilating the placement of such graphs; and present preliminary results of applying the algorithm to synthetic test cases. The method appears to result in successful and meaningful graph dilation and could be further tuned to satisfy desired power constraints.
Cite as

Branislav Hredzak and Oliver Diessel. Towards Dilated Placement of Dynamic NoC Cores. In Dynamically Reconfigurable Architectures. Dagstuhl Seminar Proceedings, Volume 10281, pp. 1-18, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2010)

Copy BibTex To Clipboard

@InProceedings{hredzak_et_al:DagSemProc.10281.14,
  author =	{Hredzak, Branislav and Diessel, Oliver},
  title =	{{Towards Dilated Placement of Dynamic NoC Cores}},
  booktitle =	{Dynamically Reconfigurable Architectures},
  pages =	{1--18},
  series =	{Dagstuhl Seminar Proceedings (DagSemProc)},
  ISSN =	{1862-4405},
  year =	{2010},
  volume =	{10281},
  editor =	{Peter M. Athanas and J\"{u}rgen Becker and J\"{u}rgen Teich and Ingrid Verbauwhede},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/DagSemProc.10281.14},
  URN =		{urn:nbn:de:0030-drops-28344},
  doi =		{10.4230/DagSemProc.10281.14},
  annote =	{Keywords: Modular reconfiguration, networks-on-chip, application mapping, dilation}
}

Filters

  • Authors
  • A
  • Abel, Norbert
  • Athanas, Peter M.
  • B
  • Baaij, Christiaan P. R.
  • Becker, Jürgen
  • Berekovic, Mladen
  • Braeken, An
  • C
  • Campos, Juan Manuel
  • Chen, Xiaolei
  • Claus, Christopher
  • Cumplido, Rene
  • D
  • Diessel, Oliver
  • F
  • Feregrino-Uribe, Claudia
  • H
  • Ha, Yajun
  • Hanke, Matthias
  • Hildenbrand, Dietmar
  • Hredzak, Branislav
  • Huthmann, Jens
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  • Kranich, Tim
  • Kuper, Jan
  • L
  • Laika, Andreas
  • M
  • Mentens, Nele
  • Müller, Peter
  • P
  • Papaefstathiou, Yannis
  • Perez-Andrade, Jose Roberto
  • S
  • Smit, Gerard J. M.
  • Stechele, Walter
  • Stock, Florian
  • T
  • Teich, Jürgen
  • Torresen, Jim
  • Touhafi, Abdellah
  • V
  • Verbauwhede, Ingrid
  • Vliegen, Jo
  • W
  • Wouters, Karel
  • Z
  • Ziener, Daniel

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