28 Search Results for "Benini, Luca"

Document
DOI: 10.4230/LIPIcs.FSTTCS.2025.25
On the Interplay of Cube Learning and Dependency Schemes in {QCDCL} Proof Systems

Authors: Abhimanyu Choudhury and Meena Mahajan

Published in: LIPIcs, Volume 360, 45th IARCS Annual Conference on Foundations of Software Technology and Theoretical Computer Science (FSTTCS 2025)

Abstract
Quantified Conflict Driven Clause Leaning (QCDCL) is one of the main approaches to solving Quantified Boolean Formulas (QBF). Cube-learning is employed in this approach to ensure that true formulas can be verified. Dependency Schemes help to detect spurious dependencies that are implied by the variable ordering in the quantifier prefix of QBFs but are not essential for constructing (counter)models. This detection can provably shorten refutations in specific proof systems, and is expected to speed up runs of QBF solvers. The simplest underlying proof system [BeyersdorffBöhm-LMCS2023], formalises the reasoning in the QCDCL approach on false formulas, when neither cube-learning nor dependency schemes is used. The work of [BöhmPeitlBeyersdorff-AI2024] further incorporates cube-learning. The work of [ChoudhuryMahajan-JAR2024] incorporates a limited use of dependency schemes, but without cube-learning. In this work, proof systems underlying the reasoning of QCDCL solvers which use cube learning, and which use dependency schemes at all stages, are formalised. Sufficient conditions for soundness and completeness are presented, and it is shown that using the standard and reflexive resolution path dependency schemes (𝙳^{std} and 𝙳^{rrs}) to relax the decision order provably shortens refutations. When the decisions are restricted to follow quantification order, but dependency schemes are used in propagation and learning, in conjunction with cube-learning, the resulting proof systems using the dependency schemes 𝙳^{std} and 𝙳^{rrs} are investigated in detail and their relative strengths are analysed.
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Abhimanyu Choudhury and Meena Mahajan. On the Interplay of Cube Learning and Dependency Schemes in {QCDCL} Proof Systems. In 45th IARCS Annual Conference on Foundations of Software Technology and Theoretical Computer Science (FSTTCS 2025). Leibniz International Proceedings in Informatics (LIPIcs), Volume 360, pp. 25:1-25:19, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2025)

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@InProceedings{choudhury_et_al:LIPIcs.FSTTCS.2025.25,
  author =	{Choudhury, Abhimanyu and Mahajan, Meena},
  title =	{{On the Interplay of Cube Learning and Dependency Schemes in \{QCDCL\} Proof Systems}},
  booktitle =	{45th IARCS Annual Conference on Foundations of Software Technology and Theoretical Computer Science (FSTTCS 2025)},
  pages =	{25:1--25:19},
  series =	{Leibniz International Proceedings in Informatics (LIPIcs)},
  ISBN =	{978-3-95977-406-2},
  ISSN =	{1868-8969},
  year =	{2025},
  volume =	{360},
  editor =	{Aiswarya, C. and Mehta, Ruta and Roy, Subhajit},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/LIPIcs.FSTTCS.2025.25},
  URN =		{urn:nbn:de:0030-drops-251062},
  doi =		{10.4230/LIPIcs.FSTTCS.2025.25},
  annote =	{Keywords: QBF, CDCL, Resolution, Dependency schemes}
}
Document
DOI: 10.4230/LIPIcs.SAT.2025.22
Enumerating All Boolean Matches

Authors: Alexander Nadel and Yogev Shalmon

Published in: LIPIcs, Volume 341, 28th International Conference on Theory and Applications of Satisfiability Testing (SAT 2025)

Abstract
Boolean matching, a fundamental problem in circuit design, determines whether two Boolean circuits are equivalent under input/output permutations and negations. While most works focus on finding a single match or proving its absence, the problem of enumerating all matches remains largely unexplored, with BooM being a notable exception. Motivated by timing challenges in Intel’s library mapping flow, we introduce EBat - an open-source tool for enumerating all matches between single-output circuits. Built from scratch, EBat reuses BooM’s SAT encoding and introduces novel high-level algorithms and performance-critical subroutines to efficiently identify and block multiple mismatches and matches simultaneously. Experiments demonstrate that EBat substantially outperforms BooM’s baseline algorithm, solving 3 to 4 times more benchmarks within a given time limit. EBat has been productized as part of Intel’s library mapping flow, effectively addressing the timing challenges.
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Alexander Nadel and Yogev Shalmon. Enumerating All Boolean Matches. In 28th International Conference on Theory and Applications of Satisfiability Testing (SAT 2025). Leibniz International Proceedings in Informatics (LIPIcs), Volume 341, pp. 22:1-22:21, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2025)

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@InProceedings{nadel_et_al:LIPIcs.SAT.2025.22,
  author =	{Nadel, Alexander and Shalmon, Yogev},
  title =	{{Enumerating All Boolean Matches}},
  booktitle =	{28th International Conference on Theory and Applications of Satisfiability Testing (SAT 2025)},
  pages =	{22:1--22:21},
  series =	{Leibniz International Proceedings in Informatics (LIPIcs)},
  ISBN =	{978-3-95977-381-2},
  ISSN =	{1868-8969},
  year =	{2025},
  volume =	{341},
  editor =	{Berg, Jeremias and Nordstr\"{o}m, Jakob},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/LIPIcs.SAT.2025.22},
  URN =		{urn:nbn:de:0030-drops-237568},
  doi =		{10.4230/LIPIcs.SAT.2025.22},
  annote =	{Keywords: Boolean Matching, All-Boolean-Matching, Enumeration, SAT, Generalization}
}
Document
DOI: 10.4230/LIPIcs.ECRTS.2025.18
Per-Flow Performance Guarantees in Networked Systems with Complex Feedback Structures

Authors: Anja Hamscher, Lukas Wildberger, and Jens Schmitt

Published in: LIPIcs, Volume 335, 37th Euromicro Conference on Real-Time Systems (ECRTS 2025)

Abstract
Many modern networked real-time systems encompass complex feedback structures and require stringent timing guarantees, especially bounds on the network delay. Network Calculus (NC) is a versatile methodology to compute such performance guarantees per individual flow; in particular, some fundamental results on how to deal with feedback exist. Yet, these are restricted to simple feedback structures and are mostly constrained to an analysis at the aggregate level (not per flow). In our work, we analyze more complex feedback structures than previously investigated by reducing them to canonical structures. We transform these closed-loop systems (with feedback) into open-loop systems (without feedback) and, subsequently, perform a per-flow analysis exploiting very recent NC results on per-flow performance guarantees. In a numerical experiment, we compare our new method to the current state-of-the-art which only allows for an aggregate FIFO analysis. We also compute how feedback constraints need to be allocated to ensure that a feedback system provides the same service as the system without feedback, in a sense providing for an optimal control. Furthermore, we compare different allocation strategies under a fixed budget for the feedback constraints.
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Anja Hamscher, Lukas Wildberger, and Jens Schmitt. Per-Flow Performance Guarantees in Networked Systems with Complex Feedback Structures. In 37th Euromicro Conference on Real-Time Systems (ECRTS 2025). Leibniz International Proceedings in Informatics (LIPIcs), Volume 335, pp. 18:1-18:25, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2025)

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@InProceedings{hamscher_et_al:LIPIcs.ECRTS.2025.18,
  author =	{Hamscher, Anja and Wildberger, Lukas and Schmitt, Jens},
  title =	{{Per-Flow Performance Guarantees in Networked Systems with Complex Feedback Structures}},
  booktitle =	{37th Euromicro Conference on Real-Time Systems (ECRTS 2025)},
  pages =	{18:1--18:25},
  series =	{Leibniz International Proceedings in Informatics (LIPIcs)},
  ISBN =	{978-3-95977-377-5},
  ISSN =	{1868-8969},
  year =	{2025},
  volume =	{335},
  editor =	{Mancuso, Renato},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2025.18},
  URN =		{urn:nbn:de:0030-drops-235961},
  doi =		{10.4230/LIPIcs.ECRTS.2025.18},
  annote =	{Keywords: Real-Time Networks, Network Calculus, Feedback Control}
}
Document
DOI: 10.4230/OASIcs.NG-RES.2025.4
H-MBR: Hypervisor-Level Memory Bandwidth Reservation for Mixed Criticality Systems

Authors: Afonso Oliveira, Diogo Costa, Gonçalo Moreira, José Martins, and Sandro Pinto

Published in: OASIcs, Volume 128, Sixth Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2025)

Abstract
Recent advancements in fields such as automotive and aerospace have driven a growing demand for robust computational resources. Applications that were once designed for basic Microcontroller Units (MCUs) are now deployed on highly heterogeneous System-on-Chip (SoC) platforms. While these platforms deliver the necessary computational performance, they also present challenges related to resource sharing and predictability. These challenges are particularly pronounced when consolidating safety-critical and non-safety-critical systems, the so-called Mixed-Criticality Systems (MCS) to adhere to strict Size, Weight, Power, and Cost (SWaP-C) requirements. MCS consolidation on shared platforms requires stringent spatial and temporal isolation to comply with functional safety standards (e.g., ISO 26262). Virtualization, mainly leveraged by hypervisors, is a key technology that ensures spatial isolation across multiple OSes and applications; however ensuring temporal isolation remains challenging due to contention on shared resources, such as main memory, caches, and system buses, which impacts real-time performance and predictability. To mitigate this problem, several strategies (e.g., cache coloring and memory bandwidth reservation) have been proposed. Although cache coloring is typically implemented on state-of-the-art hypervisors, memory bandwidth reservation approaches are commonly implemented at the Linux kernel level or rely on dedicated hardware and typically do not consider the concept of Virtual Machines that can run different OSes. To fill the gap between current memory bandwidth reservation solutions and the deployment of MCSs that operate on a hypervisor, this work introduces H-MBR, an open-source VM-centric memory bandwidth reservation mechanism. H-MBR features (i) VM-centric bandwidth reservation, (ii) OS and platform agnosticism, and (iii) reduced overhead. Empirical results evidenced no overhead on non-regulated workloads, and negligible overhead (<1%) for regulated workloads for regulation periods of 2 µs or higher.
Cite as

Afonso Oliveira, Diogo Costa, Gonçalo Moreira, José Martins, and Sandro Pinto. H-MBR: Hypervisor-Level Memory Bandwidth Reservation for Mixed Criticality Systems. In Sixth Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2025). Open Access Series in Informatics (OASIcs), Volume 128, pp. 4:1-4:15, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2025)

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@InProceedings{oliveira_et_al:OASIcs.NG-RES.2025.4,
  author =	{Oliveira, Afonso and Costa, Diogo and Moreira, Gon\c{c}alo and Martins, Jos\'{e} and Pinto, Sandro},
  title =	{{H-MBR: Hypervisor-Level Memory Bandwidth Reservation for Mixed Criticality Systems}},
  booktitle =	{Sixth Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2025)},
  pages =	{4:1--4:15},
  series =	{Open Access Series in Informatics (OASIcs)},
  ISBN =	{978-3-95977-366-9},
  ISSN =	{2190-6807},
  year =	{2025},
  volume =	{128},
  editor =	{Yomsi, Patrick Meumeu and Wildermann, Stefan},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.NG-RES.2025.4},
  URN =		{urn:nbn:de:0030-drops-229905},
  doi =		{10.4230/OASIcs.NG-RES.2025.4},
  annote =	{Keywords: Virtualization, Multi-core Interference, Mixed-Criticality Systems, Arm, Memory Bandwidth Reservation}
}
Document
DOI: 10.4230/OASIcs.NG-RES.2025.2
Low-Latency Real-Time Applications on Heterogeneous MPSoCs

Authors: Nicolas Coppik, Pascal Becker, and Marcus Ritter

Published in: OASIcs, Volume 128, Sixth Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2025)

Abstract
Heterogeneous Multi-Processor Systems-on-Chip (MPSoCs) that combine multiple, heterogeneous processing units are becoming increasingly popular for a wide range of applications, including industrial applications, where complex real-time applications can benefit from the performance and flexibility they offer. However, deploying real-time applications with low latency requirements across multiple processing units on such MPSoCs remains a challenging problem, particularly when communication between processors is required on a time-critical path. Existing solutions generally rely on the presence of at least one full-featured, general-purpose operating system on the device, and do not cater to the requirements of distributed, low-latency real-time applications. In this paper, we investigate the performance, with a focus on latency, of different options for communication between CPUs, including inter-processor interrupts and shared memory communication via different memories, on the popular Xilinx Zynq UltraScale+ platform and propose a novel solution for communication between heterogeneous processing units that relies only on the availability of shared memory. Our solution is capable of achieving sub-microsecond latencies for signaling and the transfer of small amounts of data between processing units, making it suitable for deploying distributed, low-latency real-time applications.
Cite as

Nicolas Coppik, Pascal Becker, and Marcus Ritter. Low-Latency Real-Time Applications on Heterogeneous MPSoCs. In Sixth Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2025). Open Access Series in Informatics (OASIcs), Volume 128, pp. 2:1-2:14, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2025)

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@InProceedings{coppik_et_al:OASIcs.NG-RES.2025.2,
  author =	{Coppik, Nicolas and Becker, Pascal and Ritter, Marcus},
  title =	{{Low-Latency Real-Time Applications on Heterogeneous MPSoCs}},
  booktitle =	{Sixth Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2025)},
  pages =	{2:1--2:14},
  series =	{Open Access Series in Informatics (OASIcs)},
  ISBN =	{978-3-95977-366-9},
  ISSN =	{2190-6807},
  year =	{2025},
  volume =	{128},
  editor =	{Yomsi, Patrick Meumeu and Wildermann, Stefan},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.NG-RES.2025.2},
  URN =		{urn:nbn:de:0030-drops-229883},
  doi =		{10.4230/OASIcs.NG-RES.2025.2},
  annote =	{Keywords: real-time systems, heterogeneous systems, latency, inter-core communication}
}
Document
DOI: 10.4230/OASIcs.PARMA-DITAM.2025.1
Analysis of GPU Memory Allocation Characteristics

Authors: Marcos Rodriguez, Irune Yarza, Leonidas Kosmidis, and Alejandro J. Calderón

Published in: OASIcs, Volume 127, 16th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 14th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms (PARMA-DITAM 2025)

Abstract
The number of applications subject to safety-critical regulations is on the rise, and consequently, the computing requirements for such applications are increasing as well. This trend has led to the integration of General-Purpose Graphics Processing Units (GPGPUs) into these systems. However, the inherent characteristics of GPGPUs, including their black-box nature, dynamic allocation mechanisms, and frequent use of pointers, present challenges in certifying these applications for safety-critical systems. This paper aims to shed light on the unique characteristics of GPU programs and how they impact the certification process. To achieve this goal, several allocation methods are rigorously evaluated to determine which one is best suited to an application, regarding the program characteristics within the safety-critical domain. By conducting this evaluation, we seek to provide insights into the complexities of GPU memory accesses and its compatibility with safety-critical requirements. The ultimate objective is to offer recommendations on the most appropriate allocation method based on the unique needs of each application, thus contributing to the safe and reliable integration of GPGPUs into safety-critical systems.
Cite as

Marcos Rodriguez, Irune Yarza, Leonidas Kosmidis, and Alejandro J. Calderón. Analysis of GPU Memory Allocation Characteristics. In 16th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 14th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms (PARMA-DITAM 2025). Open Access Series in Informatics (OASIcs), Volume 127, pp. 1:1-1:15, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2025)

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@InProceedings{rodriguez_et_al:OASIcs.PARMA-DITAM.2025.1,
  author =	{Rodriguez, Marcos and Yarza, Irune and Kosmidis, Leonidas and Calder\'{o}n, Alejandro J.},
  title =	{{Analysis of GPU Memory Allocation Characteristics}},
  booktitle =	{16th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 14th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms (PARMA-DITAM 2025)},
  pages =	{1:1--1:15},
  series =	{Open Access Series in Informatics (OASIcs)},
  ISBN =	{978-3-95977-363-8},
  ISSN =	{2190-6807},
  year =	{2025},
  volume =	{127},
  editor =	{Cattaneo, Daniele and Fazio, Maria and Kosmidis, Leonidas and Morabito, Gabriele},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.PARMA-DITAM.2025.1},
  URN =		{urn:nbn:de:0030-drops-229057},
  doi =		{10.4230/OASIcs.PARMA-DITAM.2025.1},
  annote =	{Keywords: CUDA, Memory allocation, Rodinia, Embedded}
}
Document
DOI: 10.4230/OASIcs.PARMA-DITAM.2025.2
Custom Floating-Point Computations for the Optimization of ODE Solvers on FPGA

Authors: Serena Curzel and Marco Gribaudo

Published in: OASIcs, Volume 127, 16th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 14th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms (PARMA-DITAM 2025)

Abstract
Mean Field Analysis and Markovian Agents are powerful techniques for modeling complex systems of distributed interacting objects, for which efficient analytical and numerical solution algorithms can be implemented through linear systems of ordinary differential equations (ODEs). Solving such ODE systems on Field Programmable Gate Arrays (FPGAs) is a promising alternative to traditional CPU- and GPU-based approaches, especially in terms of energy consumption; however, the floating-point computations required are generally thought to be slow and inefficient when implemented on FPGA. In this paper, we demonstrate the use of High-Level Synthesis with automated customization of low-precision floating-point calculations, obtaining hardware accelerators for ODE solvers with improved quality of results and minimal output error. The proposed methodology does not require any manual rewriting of the solver code, but it remains prohibitively slow to evaluate any possible floating-point configuration through logic synthesis; in the future, we will thus implement automated design space exploration methods able to suggest promising configurations under user-defined accuracy and performance constraints.
Cite as

Serena Curzel and Marco Gribaudo. Custom Floating-Point Computations for the Optimization of ODE Solvers on FPGA. In 16th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 14th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms (PARMA-DITAM 2025). Open Access Series in Informatics (OASIcs), Volume 127, pp. 2:1-2:13, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2025)

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@InProceedings{curzel_et_al:OASIcs.PARMA-DITAM.2025.2,
  author =	{Curzel, Serena and Gribaudo, Marco},
  title =	{{Custom Floating-Point Computations for the Optimization of ODE Solvers on FPGA}},
  booktitle =	{16th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 14th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms (PARMA-DITAM 2025)},
  pages =	{2:1--2:13},
  series =	{Open Access Series in Informatics (OASIcs)},
  ISBN =	{978-3-95977-363-8},
  ISSN =	{2190-6807},
  year =	{2025},
  volume =	{127},
  editor =	{Cattaneo, Daniele and Fazio, Maria and Kosmidis, Leonidas and Morabito, Gabriele},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/OASIcs.PARMA-DITAM.2025.2},
  URN =		{urn:nbn:de:0030-drops-229064},
  doi =		{10.4230/OASIcs.PARMA-DITAM.2025.2},
  annote =	{Keywords: Differential Equations, High-Level Synthesis, FPGA, floating-point}
}
Document
DOI: 10.4230/LITES-v003-i001-a003
Modeling Power Consumption and Temperature in TLM Models

Authors: Matthieu Moy, Claude Helmstetter, Tayeb Bouhadiba, and Florence Maraninchi

Published in: LITES, Volume 3, Issue 1 (2016). Leibniz Transactions on Embedded Systems, Volume 3, Issue 1

Abstract
Many techniques and tools exist to estimate the power consumption and the temperature map of a chip. These tools help the hardware designers develop power efficient chips in the presence of temperature constraints. For this task, the application can be ignored or at least abstracted by some high level scenarios; at this stage, the actual embedded software is generally not available yet.However, after the hardware is defined, the embedded software can still have a significant influence on the power consumption; i.e., two implementations of the same application can consume more or less power. Moreover, the actual software power manager ensuring the temperature constraints, usually by acting dynamically on the voltage and frequency, must itself be validated. Validating such power management policy requires a model of both actuators and sensors, hence a closed-loop simulation of the functional model with a non-functional one.In this paper, we present and compare several tools to simulate the power and thermal behavior of a chip together with its functionality. We explore several levels of abstraction and study the impact on the precision of the analysis.
Cite as

Matthieu Moy, Claude Helmstetter, Tayeb Bouhadiba, and Florence Maraninchi. Modeling Power Consumption and Temperature in TLM Models. In LITES, Volume 3, Issue 1 (2016). Leibniz Transactions on Embedded Systems, Volume 3, Issue 1, pp. 03:1-03:29, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2016)

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@Article{moy_et_al:LITES-v003-i001-a003,
  author =	{Moy, Matthieu and Helmstetter, Claude and Bouhadiba, Tayeb and Maraninchi, Florence},
  title =	{{Modeling Power Consumption and Temperature in TLM Models}},
  journal =	{Leibniz Transactions on Embedded Systems},
  pages =	{03:1--03:29},
  ISSN =	{2199-2002},
  year =	{2016},
  volume =	{3},
  number =	{1},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/LITES-v003-i001-a003},
  URN =		{urn:nbn:de:0030-drops-192584},
  doi =		{10.4230/LITES-v003-i001-a003},
  annote =	{Keywords: Power consumption, Temperature control, Virtual prototype, SystemC, Transactional modeling}
}
Document
DOI: 10.4230/DagSemProc.07041.1
07041 Abstracts Collection – Power-aware Computing Systems

Authors: Luca Benini, Naehyuck Chang, Ulrich Kremer, and Christian W. Probst

Published in: Dagstuhl Seminar Proceedings, Volume 7041, Power-aware Computing Systems (2007)

Abstract
From January 21, 2007 to January 26, 2007, the Dagstuhl Seminar 07041``Power-aware Computing Systems'' was held in the International Conference and Research Center (IBFI), Schloss Dagstuhl. During the seminar, several participants presented their current research, and discussed ongoing work and open problems. This report compiles abstracts of the seminar presentations as well as the seminar results and ideas, providing hyperlinks to full papers wherever possible.
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Luca Benini, Naehyuck Chang, Ulrich Kremer, and Christian W. Probst. 07041 Abstracts Collection – Power-aware Computing Systems. In Power-aware Computing Systems. Dagstuhl Seminar Proceedings, Volume 7041, pp. 1-14, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2007)

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@InProceedings{benini_et_al:DagSemProc.07041.1,
  author =	{Benini, Luca and Chang, Naehyuck and Kremer, Ulrich and Probst, Christian W.},
  title =	{{07041 Abstracts Collection – Power-aware Computing Systems}},
  booktitle =	{Power-aware Computing Systems},
  pages =	{1--14},
  series =	{Dagstuhl Seminar Proceedings (DagSemProc)},
  ISSN =	{1862-4405},
  year =	{2007},
  volume =	{7041},
  editor =	{Luca Benini and Naehyuck Chang and Ulrich Kremer and Christian W. Probst},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/DagSemProc.07041.1},
  URN =		{urn:nbn:de:0030-drops-11248},
  doi =		{10.4230/DagSemProc.07041.1},
  annote =	{Keywords: Power consumption, energy reduction, compilers, microarchitectures, simulations, experimental frameworks}
}
Document
DOI: 10.4230/DagSemProc.07041.2
07041 Summary – Power-aware Computing Systems

Authors: Luca Benini, Naehyuck Chang, Ulrich Kremer, and Christian W. Probst

Published in: Dagstuhl Seminar Proceedings, Volume 7041, Power-aware Computing Systems (2007)

Abstract
The program of the Dagstuhl seminar 07041 on Power-aware Computing Systems featured presentations of about 25 participating researchers from academia and industry. They were chosen to represent major areas in targeting the energy consumption of a computing system – Applications, Compilers, Virtual-execution Environments, Operating Systems, and Hardware. In order to continue the work of the predecessor Dagstuhl seminar held in 2005, the results of that seminar [1] were discussed, with the aim of developing a vision of challenges, problems, and research activities in some of the key areas identified in 2005. The first part of the seminar was dedicated to lively discussions that led to the identification of three areas that were considered being most interesting. As a result, three groups were formed to further identify challenges and opportunities. The results of these groups are presented in this report. In addition, abstracts of the presentations as well as work-in-progress papers are published in these proceedings.
Cite as

Luca Benini, Naehyuck Chang, Ulrich Kremer, and Christian W. Probst. 07041 Summary – Power-aware Computing Systems. In Power-aware Computing Systems. Dagstuhl Seminar Proceedings, Volume 7041, pp. 1-7, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2007)

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@InProceedings{benini_et_al:DagSemProc.07041.2,
  author =	{Benini, Luca and Chang, Naehyuck and Kremer, Ulrich and Probst, Christian W.},
  title =	{{07041 Summary – Power-aware Computing Systems}},
  booktitle =	{Power-aware Computing Systems},
  pages =	{1--7},
  series =	{Dagstuhl Seminar Proceedings (DagSemProc)},
  ISSN =	{1862-4405},
  year =	{2007},
  volume =	{7041},
  editor =	{Luca Benini and Naehyuck Chang and Ulrich Kremer and Christian W. Probst},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/DagSemProc.07041.2},
  URN =		{urn:nbn:de:0030-drops-11232},
  doi =		{10.4230/DagSemProc.07041.2},
  annote =	{Keywords: Power-aware Computing Systems, Low-power Design, Parallelism and Power Consumption}
}
Document
DOI: 10.4230/DagSemProc.07041.3
07041 Working Group – Towards Interfaces for Integrated Performance and Power Analysis and Simulation

Authors: Chris Bleakley, Tom Clerckx, Harald Devos, Matthias Grumer, Alex Janek, Ulrich Kremer, Christian W. Probst, Phillip Stanley-Marbell, Christian Steger, Vasanth Venkatachalam, and Manuel Wendt

Published in: Dagstuhl Seminar Proceedings, Volume 7041, Power-aware Computing Systems (2007)

Abstract
In the design and optimization of power-aware computing systems, it is often desired to estimate power consumption at various levels of abstraction, e.g., at the transistor, gate, RTL, behavioral or transaction levels. Tools for power estimation at these different levels of abstraction require specialized expertise, e.g., understanding of device physics for circuit-level power estimation, and as such are necessarily developed by different research communities. In the optimization of complete platforms however, it is desired to be able to obtain aggregate power and performance estimates for the different components of a system, and this requires the ability to model the system at a mixture of levels of abstraction. One approach to enabling such cross-abstraction modeling, is to define a mechanism for interchange of data between tools at different layers of abstraction, for both static analysis and simulation-based studies. This document presents preliminary discussions on the requirements of such an interface.
Cite as

Chris Bleakley, Tom Clerckx, Harald Devos, Matthias Grumer, Alex Janek, Ulrich Kremer, Christian W. Probst, Phillip Stanley-Marbell, Christian Steger, Vasanth Venkatachalam, and Manuel Wendt. 07041 Working Group – Towards Interfaces for Integrated Performance and Power Analysis and Simulation. In Power-aware Computing Systems. Dagstuhl Seminar Proceedings, Volume 7041, pp. 1-6, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2007)

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@InProceedings{bleakley_et_al:DagSemProc.07041.3,
  author =	{Bleakley, Chris and Clerckx, Tom and Devos, Harald and Grumer, Matthias and Janek, Alex and Kremer, Ulrich and Probst, Christian W. and Stanley-Marbell, Phillip and Steger, Christian and Venkatachalam, Vasanth and Wendt, Manuel},
  title =	{{07041 Working Group – Towards Interfaces for Integrated Performance and Power Analysis and Simulation}},
  booktitle =	{Power-aware Computing Systems},
  pages =	{1--6},
  series =	{Dagstuhl Seminar Proceedings (DagSemProc)},
  ISSN =	{1862-4405},
  year =	{2007},
  volume =	{7041},
  editor =	{Luca Benini and Naehyuck Chang and Ulrich Kremer and Christian W. Probst},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/DagSemProc.07041.3},
  URN =		{urn:nbn:de:0030-drops-11072},
  doi =		{10.4230/DagSemProc.07041.3},
  annote =	{Keywords: Power Estimation Tools, Simulation, Tool Interfaces}
}
Document
DOI: 10.4230/DagSemProc.07041.4
Automist - A Tool for Automated Instruction Set Characterization of Embedded Processors

Authors: Manuel Wendt, Matthias Grumer, Christian Steger, and Ulrich Neffe

Published in: Dagstuhl Seminar Proceedings, Volume 7041, Power-aware Computing Systems (2007)

Abstract
The steadily increasing performance of mobile devices also implies a rise in power consumption. To counteract this trend it is mandatory to accomplish software power optimizations based on accurate power consumption models characterized for the processor. This paper presents an environment for automated instruction set characterization based on physical power measurements. Based on a detailed instruction set description a testbench generator creates all needed test programs for a complete characterization. Afterwards those programs are executed by the processor and the energy consumption is measured. For an accurate energy measurement a high performance sampling technique has been established, which can be either clock or energy driven.
Cite as

Manuel Wendt, Matthias Grumer, Christian Steger, and Ulrich Neffe. Automist - A Tool for Automated Instruction Set Characterization of Embedded Processors. In Power-aware Computing Systems. Dagstuhl Seminar Proceedings, Volume 7041, pp. 1-10, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2007)

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@InProceedings{wendt_et_al:DagSemProc.07041.4,
  author =	{Wendt, Manuel and Grumer, Matthias and Steger, Christian and Neffe, Ulrich},
  title =	{{Automist - A Tool for Automated Instruction Set Characterization of Embedded Processors}},
  booktitle =	{Power-aware Computing Systems},
  pages =	{1--10},
  series =	{Dagstuhl Seminar Proceedings (DagSemProc)},
  ISSN =	{1862-4405},
  year =	{2007},
  volume =	{7041},
  editor =	{Luca Benini and Naehyuck Chang and Ulrich Kremer and Christian W. Probst},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/DagSemProc.07041.4},
  URN =		{urn:nbn:de:0030-drops-11097},
  doi =		{10.4230/DagSemProc.07041.4},
  annote =	{Keywords: Software energy estimation, automated processor characterization, testbench generator, current measurement, clock driven sampling, energy driven sampl}
}
Document
DOI: 10.4230/DagSemProc.07041.5
Compiler-based Software Power Peak Elimination on Smart Card Systems

Authors: Matthias Grumer, Manuel Wendt, Christian Steger, Reinhold Weiss, Ulrich Neffe, and Andreas Muehlberger

Published in: Dagstuhl Seminar Proceedings, Volume 7041, Power-aware Computing Systems (2007)

Abstract
RF-powered smart cards are widely used in different application areas today. For smart cards not only performance is an important attribute, but also the power consumed by a given application. The power consumed is heavily depending on the software executed on the system. The power profile, especially the power peaks, of an executed application influence the system stability and security. Flattening the power profile can thus increase the stability and security of a system. In this paper we present an optimization system that allows a reduction of power peaks based on a compiler optimization. The optimizations are done on different levels of the compiler. In the backend of the compiler we present new instruction scheduling algorithms. On the intermediate language level we propose the use of iterative compiling for reducing critical peaks.
Cite as

Matthias Grumer, Manuel Wendt, Christian Steger, Reinhold Weiss, Ulrich Neffe, and Andreas Muehlberger. Compiler-based Software Power Peak Elimination on Smart Card Systems. In Power-aware Computing Systems. Dagstuhl Seminar Proceedings, Volume 7041, pp. 1-9, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2007)

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@InProceedings{grumer_et_al:DagSemProc.07041.5,
  author =	{Grumer, Matthias and Wendt, Manuel and Steger, Christian and Weiss, Reinhold and Neffe, Ulrich and Muehlberger, Andreas},
  title =	{{Compiler-based Software Power Peak Elimination on Smart Card Systems}},
  booktitle =	{Power-aware Computing Systems},
  pages =	{1--9},
  series =	{Dagstuhl Seminar Proceedings (DagSemProc)},
  ISSN =	{1862-4405},
  year =	{2007},
  volume =	{7041},
  editor =	{Luca Benini and Naehyuck Chang and Ulrich Kremer and Christian W. Probst},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/DagSemProc.07041.5},
  URN =		{urn:nbn:de:0030-drops-11030},
  doi =		{10.4230/DagSemProc.07041.5},
  annote =	{Keywords: Software power optimization, compiler optimization, peak reduction}
}
Document
DOI: 10.4230/DagSemProc.07041.6
Complexity of Scheduling in Synthesizing Hardware from Concurrent Action Oriented Specifications

Authors: Gaurav Singh, S. S. Ravi, Sumit Ahuja, and Sandeep Shukla

Published in: Dagstuhl Seminar Proceedings, Volume 7041, Power-aware Computing Systems (2007)

Abstract
Concurrent Action Oriented Specifications (CAOS) formalism such as Bluespec Inc.'s Bluespec System Verilog (BSV) has been recently shown to be effective for hardware modeling and synthesis. This formalism offers the benefits of automatic handling of concurrency issues in highly concurrent system descriptions, and the associated synthesis algorithms have been shown to produce efficient hardware comparable to those generated from hand-written Verilog/VHDL. These benefits which are inherent in such a synthesis process also aid in faster architectural exploration. This is because CAOS allows a high-level description (above RTL) of a design in terms of atomic transactions, where each transaction corresponds to a collection of operations. Optimal scheduling of such actions in CAOS-based synthesis process is crucial in order to generate hardware that is efficient in terms of area, latency and power. In this paper, we analyze the complexity of the scheduling problems associated with CAOS-based synthesis and discuss several heuristics for meeting the peak power goals of designs generated from CAOS. We also discuss approximability of these problems as appropriate.
Cite as

Gaurav Singh, S. S. Ravi, Sumit Ahuja, and Sandeep Shukla. Complexity of Scheduling in Synthesizing Hardware from Concurrent Action Oriented Specifications. In Power-aware Computing Systems. Dagstuhl Seminar Proceedings, Volume 7041, pp. 1-25, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2007)

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@InProceedings{singh_et_al:DagSemProc.07041.6,
  author =	{Singh, Gaurav and Ravi, S. S. and Ahuja, Sumit and Shukla, Sandeep},
  title =	{{Complexity of Scheduling in Synthesizing Hardware from Concurrent Action Oriented Specifications}},
  booktitle =	{Power-aware Computing Systems},
  pages =	{1--25},
  series =	{Dagstuhl Seminar Proceedings (DagSemProc)},
  ISSN =	{1862-4405},
  year =	{2007},
  volume =	{7041},
  editor =	{Luca Benini and Naehyuck Chang and Ulrich Kremer and Christian W. Probst},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/DagSemProc.07041.6},
  URN =		{urn:nbn:de:0030-drops-11055},
  doi =		{10.4230/DagSemProc.07041.6},
  annote =	{Keywords: Hardware Synthesis, Concurrent Action Oriented Specifications (CAOS), Scheduling, Complexity, Peak Power.}
}
Document
DOI: 10.4230/DagSemProc.07041.7
Electrocardiogram on Wireless Sensor Nodes

Authors: Lennart Yseboodt, Michael De Nil, and Mladen Berekovic

Published in: Dagstuhl Seminar Proceedings, Volume 7041, Power-aware Computing Systems (2007)

Abstract
Wireless sensor nodes are applicable in a wide range of situations such as the medical, industrial or environmental domains, but the focus is on the biomedical domain. This paper presents the steps taken to develop a low power processor using Silicon Hive technology and mapping an electrocardiogram analysis algorithm on that processor. Today's energy-scavengers are able to deliver 100microwatt. This is the global power constraint of the sensor node. With a total power consumption of 16microwatt, the DSP processes the samples, compresses them into extracted parameters and the results are sent out by means of a radio.
Cite as

Lennart Yseboodt, Michael De Nil, and Mladen Berekovic. Electrocardiogram on Wireless Sensor Nodes. In Power-aware Computing Systems. Dagstuhl Seminar Proceedings, Volume 7041, pp. 1-4, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2007)

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@InProceedings{yseboodt_et_al:DagSemProc.07041.7,
  author =	{Yseboodt, Lennart and De Nil, Michael and Berekovic, Mladen},
  title =	{{Electrocardiogram on Wireless Sensor Nodes}},
  booktitle =	{Power-aware Computing Systems},
  pages =	{1--4},
  series =	{Dagstuhl Seminar Proceedings (DagSemProc)},
  ISSN =	{1862-4405},
  year =	{2007},
  volume =	{7041},
  editor =	{Luca Benini and Naehyuck Chang and Ulrich Kremer and Christian W. Probst},
  publisher =	{Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address =	{Dagstuhl, Germany},
  URL =		{https://drops.dagstuhl.de/entities/document/10.4230/DagSemProc.07041.7},
  URN =		{urn:nbn:de:0030-drops-11118},
  doi =		{10.4230/DagSemProc.07041.7},
  annote =	{Keywords: Ultra-low-power, electrocardiogram, wireless}
}
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