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LIPIcs, Volume 375
38th European Conference on Real-Time Systems (ECRTS 2026)
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Leibniz International Proceedings in Informatics (LIPIcs)
Conference: Euromicro Conference on Real-Time Systems (ECRTS)
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- published at: 2026-07-02
- Publisher: Schloss Dagstuhl – Leibniz-Zentrum für Informatik
- ISBN: 978-3-95977-429-1
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Document
Complete Volume
LIPIcs, Volume 375, ECRTS 2026, Complete Volume
Abstract
LIPIcs, Volume 375, ECRTS 2026, Complete Volume
Cite as
38th European Conference on Real-Time Systems (ECRTS 2026). Leibniz International Proceedings in Informatics (LIPIcs), Volume 375, pp. 1-570, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2026)
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@Proceedings{kritikakou:LIPIcs.ECRTS.2026,
title = {{LIPIcs, Volume 375, ECRTS 2026, Complete Volume}},
booktitle = {38th European Conference on Real-Time Systems (ECRTS 2026)},
pages = {1--570},
series = {Leibniz International Proceedings in Informatics (LIPIcs)},
ISBN = {978-3-95977-429-1},
ISSN = {1868-8969},
year = {2026},
volume = {375},
editor = {Kritikakou, Angeliki},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2026},
URN = {urn:nbn:de:0030-drops-268738},
doi = {10.4230/LIPIcs.ECRTS.2026},
annote = {Keywords: LIPIcs, Volume 375, ECRTS 2026, Complete Volume}
}
Document
Front Matter
Front Matter, Table of Contents, Preface, Conference Organization
Abstract
Front Matter, Table of Contents, Preface, Conference Organization
Cite as
38th European Conference on Real-Time Systems (ECRTS 2026). Leibniz International Proceedings in Informatics (LIPIcs), Volume 375, pp. 0:i-0:xviii, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2026)
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@InProceedings{kritikakou:LIPIcs.ECRTS.2026.0,
author = {Kritikakou, Angeliki},
title = {{Front Matter, Table of Contents, Preface, Conference Organization}},
booktitle = {38th European Conference on Real-Time Systems (ECRTS 2026)},
pages = {0:i--0:xviii},
series = {Leibniz International Proceedings in Informatics (LIPIcs)},
ISBN = {978-3-95977-429-1},
ISSN = {1868-8969},
year = {2026},
volume = {375},
editor = {Kritikakou, Angeliki},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2026.0},
URN = {urn:nbn:de:0030-drops-268722},
doi = {10.4230/LIPIcs.ECRTS.2026.0},
annote = {Keywords: Front Matter, Table of Contents, Preface, Conference Organization}
}
Document
Critical-Section Granularity for Multi-Resource Systems with Nested Critical Sections
Abstract
Typical models of resource-sharing real-time tasks provide the worst-case task execution time and the duration of each critical section during which a resource is accessed. Such models abstract away the detailed behavior of a task, which may make several individual accesses within a single critical section, incurring access overhead once for the entire critical section. Considering a more fine-grained model with individual access and non-access segments at the forefront gives more control in the system design process; choosing how accesses are grouped into critical sections enables balancing trade-offs between overhead and blocking based on other system parameters, including task deadlines. This paper presents an optimal approach for multi-resource systems that allow any given task to use up to two resources, including support for nested critical sections. This is achieved by extending analysis to multiple resources and constructing a Quadratically-Constrained Integer Program to determine critical sections. This approach is compared to heuristics on the basis of schedulability and its runtime is explored. Further extension to support more resources per task is discussed.
Cite as
Catherine E. Nemitz, Tanya Amert, and Jonad Pulaj. Critical-Section Granularity for Multi-Resource Systems with Nested Critical Sections. In 38th European Conference on Real-Time Systems (ECRTS 2026). Leibniz International Proceedings in Informatics (LIPIcs), Volume 375, pp. 1:1-1:24, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2026)
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@InProceedings{nemitz_et_al:LIPIcs.ECRTS.2026.1,
author = {Nemitz, Catherine E. and Amert, Tanya and Pulaj, Jonad},
title = {{Critical-Section Granularity for Multi-Resource Systems with Nested Critical Sections}},
booktitle = {38th European Conference on Real-Time Systems (ECRTS 2026)},
pages = {1:1--1:24},
series = {Leibniz International Proceedings in Informatics (LIPIcs)},
ISBN = {978-3-95977-429-1},
ISSN = {1868-8969},
year = {2026},
volume = {375},
editor = {Kritikakou, Angeliki},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2026.1},
URN = {urn:nbn:de:0030-drops-265859},
doi = {10.4230/LIPIcs.ECRTS.2026.1},
annote = {Keywords: Real-time systems, shared resources, fixed-priority scheduling, schedulability}
}
Document
Preempt Less, Schedule Better: Revisiting PCG for Real-Time Uniform Processors
Abstract
We address the problem of scheduling periodic implicit-deadline real-time tasks on m uniform processors. We introduce PCG^*, an optimal TL-plane algorithm based on PCG [Chen and Hsueh, 2008], which guarantees at most 2(m - 1) preemptions per TL-plane, matching the best-known theoretical bound for uniform platforms. The proposed algorithm advances the state of the art by offering an optimal real-time scheduling solution with a tight preemption bound within TL-planes. The numerical experiments presented in this work provide strong evidence that PCG^* yields a substantial reduction in the number of preemptions relative to PCG. When applied to identical processor platforms, PCG^* is also a best-possible polynomial time algorithm in terms of preemptions in a TL-plane, matching the (m-1) preemption bound achieved by LRE-TL [Funk, 2010].
Cite as
Yahya Hamdani, Pascal Richard, Antoine Bertout, Joël Goossens, and Emmanuel Grolleau. Preempt Less, Schedule Better: Revisiting PCG for Real-Time Uniform Processors. In 38th European Conference on Real-Time Systems (ECRTS 2026). Leibniz International Proceedings in Informatics (LIPIcs), Volume 375, pp. 2:1-2:23, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2026)
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@InProceedings{hamdani_et_al:LIPIcs.ECRTS.2026.2,
author = {Hamdani, Yahya and Richard, Pascal and Bertout, Antoine and Goossens, Jo\"{e}l and Grolleau, Emmanuel},
title = {{Preempt Less, Schedule Better: Revisiting PCG for Real-Time Uniform Processors}},
booktitle = {38th European Conference on Real-Time Systems (ECRTS 2026)},
pages = {2:1--2:23},
series = {Leibniz International Proceedings in Informatics (LIPIcs)},
ISBN = {978-3-95977-429-1},
ISSN = {1868-8969},
year = {2026},
volume = {375},
editor = {Kritikakou, Angeliki},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2026.2},
URN = {urn:nbn:de:0030-drops-265863},
doi = {10.4230/LIPIcs.ECRTS.2026.2},
annote = {Keywords: Real-Time Scheduling, Uniform Multiprocessor Platforms}
}
Document
Probabilistic Schedulability Analysis for Mixed-Criticality DAG Tasks on Multiprocessors
Abstract
Mixed-criticality DAG task systems on multiprocessors require schedulability analysis to guarantee that safety-critical tasks meet their deadlines. Conventional approaches rely on worst-case execution times (WCETs), which account for extremely rare pathological scenarios and consequently lead to significant over-provisioning of processor cores. This paper proposes a probabilistic schedulability analysis that exploits the statistical rarity of multiple vertices within a DAG exceeding their expected execution budgets. By grouping vertices within each DAG into small clusters and bounding the probability that more than one vertex in a cluster overruns, the method assigns each cluster a tighter execution budget than the sum of individual WCETs, thereby reducing the number of cores required. The clustering configuration is optimized via simulated annealing to minimize total core usage while maintaining a designer-specified bound on the system-level probability of deadline misses. Experiments on synthetic task sets demonstrate that the proposed method reduces the required number of cores by up to 36% compared to a deterministic baseline, with larger gains for DAGs exhibiting higher internal parallelism.
Cite as
Hiroto Takahashi, Atsushi Yano, and Takuya Azumi. Probabilistic Schedulability Analysis for Mixed-Criticality DAG Tasks on Multiprocessors. In 38th European Conference on Real-Time Systems (ECRTS 2026). Leibniz International Proceedings in Informatics (LIPIcs), Volume 375, pp. 3:1-3:23, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2026)
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@InProceedings{takahashi_et_al:LIPIcs.ECRTS.2026.3,
author = {Takahashi, Hiroto and Yano, Atsushi and Azumi, Takuya},
title = {{Probabilistic Schedulability Analysis for Mixed-Criticality DAG Tasks on Multiprocessors}},
booktitle = {38th European Conference on Real-Time Systems (ECRTS 2026)},
pages = {3:1--3:23},
series = {Leibniz International Proceedings in Informatics (LIPIcs)},
ISBN = {978-3-95977-429-1},
ISSN = {1868-8969},
year = {2026},
volume = {375},
editor = {Kritikakou, Angeliki},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2026.3},
URN = {urn:nbn:de:0030-drops-265871},
doi = {10.4230/LIPIcs.ECRTS.2026.3},
annote = {Keywords: Mixed-Criticality Systems, DAG Tasks, Probabilistic Analysis, Federated Scheduling, Real-Time Systems}
}
Document
Boost-At-The-Tail: Work-Triggered Frequency Boosting for Fixed-Priority Scheduling
Abstract
Fixed-priority (FP) scheduling is widely used in safety-critical real-time systems due to its simplicity and analyzability, yet it may fail to schedule task sets whose worst-case response-time bounds exceed deadlines by small margins. Meanwhile, modern processors increasingly support short-term frequency boosting, providing additional processing capacity subject to thermal and power constraints. This paper introduces Boosted-FP, a fixed-priority scheduling framework that augments a given FP policy with controlled, limited frequency boosting. The key idea is to activate boosting based on the worst-case remaining execution demand of the currently executing job, thereby confining high-frequency execution to the tail of jobs. Per-task boost parameters are computed offline using standard fixed-priority response-time analysis under the chosen priority assignment, while boost activation decisions are made online using worst-case remaining-work information.
We show that Boosted-FP preserves hard real-time guarantees by relating its execution behavior to that of a task set with reduced execution times. Leveraging the sustainability of fixed-priority schedulability analysis with respect to execution-time reductions, we establish that any task set schedulable under the modified execution bounds is also schedulable under the proposed framework. We evaluate the framework under a global boost-budget constraint and show experimentally that boost usage remains bounded and often well below the offline provisioned budget. Together, these results demonstrate that controlled, work-triggered boosting can safely extend the schedulable region of fixed-priority scheduling without abandoning static priorities.
Cite as
Behnam Khodabandeloo, Chengzi Huang, and Pontus Ekberg. Boost-At-The-Tail: Work-Triggered Frequency Boosting for Fixed-Priority Scheduling. In 38th European Conference on Real-Time Systems (ECRTS 2026). Leibniz International Proceedings in Informatics (LIPIcs), Volume 375, pp. 4:1-4:22, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2026)
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@InProceedings{khodabandeloo_et_al:LIPIcs.ECRTS.2026.4,
author = {Khodabandeloo, Behnam and Huang, Chengzi and Ekberg, Pontus},
title = {{Boost-At-The-Tail: Work-Triggered Frequency Boosting for Fixed-Priority Scheduling}},
booktitle = {38th European Conference on Real-Time Systems (ECRTS 2026)},
pages = {4:1--4:22},
series = {Leibniz International Proceedings in Informatics (LIPIcs)},
ISBN = {978-3-95977-429-1},
ISSN = {1868-8969},
year = {2026},
volume = {375},
editor = {Kritikakou, Angeliki},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2026.4},
URN = {urn:nbn:de:0030-drops-265884},
doi = {10.4230/LIPIcs.ECRTS.2026.4},
annote = {Keywords: Fixed Priority Scheduling, Boost frequency, Execution slack}
}
Document
Nancy-Playground: A Console Calculator for Deterministic Network Calculus
Abstract
Deterministic Network Calculus (DNC) provides a rigorous algebra for worst-case performance analysis of networks. It allows researchers to compute bounds on worst-case characteristics of systems through algebraic expressions that may appear simple on paper but often require heavy computations, making software support essential. Libraries such as Nancy offer a rich API for DNC computations in C#, but they require programming expertise. In contrast, RTaW’s min-plus playground (MPPG) provides a simpler, calculator-like syntax for DNC computations; however, it is proprietary and web-hosted, limiting offline use and reproducibility. We present nancy-playground, an open-source, locally runnable console that implements the same MPPG syntax while executing computations through the Nancy library. This tool enables reproducible scripting, interactive exploration, and a seamless transition to full programs by converting MPPG scripts into C# code. In this paper, we describe the design and implementation of nancy-playground, as well as its main features for researchers and practitioners in the DNC community.
Cite as
Raffaele Zippo and Giovanni Stea. Nancy-Playground: A Console Calculator for Deterministic Network Calculus. In 38th European Conference on Real-Time Systems (ECRTS 2026). Leibniz International Proceedings in Informatics (LIPIcs), Volume 375, pp. 5:1-5:16, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2026)
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@InProceedings{zippo_et_al:LIPIcs.ECRTS.2026.5,
author = {Zippo, Raffaele and Stea, Giovanni},
title = {{Nancy-Playground: A Console Calculator for Deterministic Network Calculus}},
booktitle = {38th European Conference on Real-Time Systems (ECRTS 2026)},
pages = {5:1--5:16},
series = {Leibniz International Proceedings in Informatics (LIPIcs)},
ISBN = {978-3-95977-429-1},
ISSN = {1868-8969},
year = {2026},
volume = {375},
editor = {Kritikakou, Angeliki},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2026.5},
URN = {urn:nbn:de:0030-drops-265970},
doi = {10.4230/LIPIcs.ECRTS.2026.5},
annote = {Keywords: Deterministic Network Calculus, min-plus algebra, tooling}
}
Document
Automated and Precise Deterministic NetCal Calculations from Models to Bounds
Abstract
The deterministic variant of Network Calculus (NetCal, NC) enables for calculating worst-case performance guarantees in communication networks. We present the NetworkCalculus.org Deterministic Network Calculator (NCorg DNC), a tool for Deterministic Network Calculus (DNC) that extends the previous DiscoDNC by significantly enhancing its capabilities for modeling and analysis of real-world applications. The tool offers a new end-to-end solution: Starting from the prevalent model of a full-duplex Ethernet-like networks with output queueing, the NCorg DNC offers automated conversion to its DNC model as well as application of state-of-the-research DNC analysis methods to derive worst-case delay bounds. Another significant step forward are new numerical capabilities that can model and analyze, among others, discrete data arrivals as well as service.
While we enhance features and capabilities, we keep the cost in terms of tool runtimes at bay. Our numerical evaluation showcases improved performance bounding w.r.t to previous DiscoDNC results and a comparative experimental tool performance study quantifying the computational impact of the added functionality. Overall, the NCorgDNC provides a more versatile and extensible foundation for deterministic performance analysis in modern networked systems.
Cite as
Wlad Pesotsky, Eric Hermsen, and Steffen Bondorf. Automated and Precise Deterministic NetCal Calculations from Models to Bounds. In 38th European Conference on Real-Time Systems (ECRTS 2026). Leibniz International Proceedings in Informatics (LIPIcs), Volume 375, pp. 6:1-6:19, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2026)
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@InProceedings{pesotsky_et_al:LIPIcs.ECRTS.2026.6,
author = {Pesotsky, Wlad and Hermsen, Eric and Bondorf, Steffen},
title = {{Automated and Precise Deterministic NetCal Calculations from Models to Bounds}},
booktitle = {38th European Conference on Real-Time Systems (ECRTS 2026)},
pages = {6:1--6:19},
series = {Leibniz International Proceedings in Informatics (LIPIcs)},
ISBN = {978-3-95977-429-1},
ISSN = {1868-8969},
year = {2026},
volume = {375},
editor = {Kritikakou, Angeliki},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2026.6},
URN = {urn:nbn:de:0030-drops-265986},
doi = {10.4230/LIPIcs.ECRTS.2026.6},
annote = {Keywords: Network Calculus, Real-Time Systems}
}
Document
Controlling Adaptive HARQ Erasure Coding for Real-Time Transport Under Channel Model Mismatch
Abstract
Networking is an essential component of real-time cyber-physical systems, and hence, networking problems are increasingly real-time problems. As these systems expand beyond single, controlled links, they require predictably reliable end-to-end communication primitives, effectively transferring their deadline constraints to the underlying multi-hop network. Standard transport protocols often optimize either only for latency (e.g., UDP) or for full reliability (e.g., TCP, QUIC), with the latter potentially leading to unbounded retransmission delays. Partial reliability bridges the gap between these extremes, offering configurable reliability within a bounded delay. To remain bandwidth-efficient and robust to dynamic network conditions, these schemes must abandon static forward error correction (FEC) and move toward adaptive loss recovery. A fundamental challenge is the model mismatch problem: real-time adaptive loss recovery schemes require simple, efficiently interpretable models to estimate network conditions, yet these models systematically underfit complex real-world network dynamics.
To provide robustness against this inherent underfitting, we present a closed-loop control architecture that applies an adaptive safety margin to the network estimates, ensuring the system meets a deadline-constrained reliability target. We frame this contribution within the Predictably Reliable Real-time Transport protocol (PRRT), which allows applications to configure a loss and deadline constraint. The control system observes the packet delivery deficit (packet debt) to quantify the extent to which the end-to-end packet-loss rate deviates from the application’s target loss rate. A compensated loss rate is then fed into a novel constraint-aware, anytime incremental search algorithm that derives a near-optimal Hybrid Automatic Repeat Request (HARQ) coding configuration that combines the benefits of proactive and reactive packet-loss recovery to satisfy the application’s loss and delay constraints. New to this search is its awareness of the encoding and decoding complexity of the resulting coding configurations. This allows devices to adaptively limit the search space to configurations within their computational capabilities, which is essential for constrained edge devices. We provide a new high-performance Rust reference implementation of PRRT and demonstrate that the system converges towards the target loss rate, even under model mismatch, while also quickly adapting to shifts in network conditions.
Cite as
Moritz Miodek, Marlene Böhmer, and Thorsten Herfet. Controlling Adaptive HARQ Erasure Coding for Real-Time Transport Under Channel Model Mismatch. In 38th European Conference on Real-Time Systems (ECRTS 2026). Leibniz International Proceedings in Informatics (LIPIcs), Volume 375, pp. 7:1-7:24, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2026)
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@InProceedings{miodek_et_al:LIPIcs.ECRTS.2026.7,
author = {Miodek, Moritz and B\"{o}hmer, Marlene and Herfet, Thorsten},
title = {{Controlling Adaptive HARQ Erasure Coding for Real-Time Transport Under Channel Model Mismatch}},
booktitle = {38th European Conference on Real-Time Systems (ECRTS 2026)},
pages = {7:1--7:24},
series = {Leibniz International Proceedings in Informatics (LIPIcs)},
ISBN = {978-3-95977-429-1},
ISSN = {1868-8969},
year = {2026},
volume = {375},
editor = {Kritikakou, Angeliki},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2026.7},
URN = {urn:nbn:de:0030-drops-265994},
doi = {10.4230/LIPIcs.ECRTS.2026.7},
annote = {Keywords: Real-time networks, transport protocol, HARQ, adaptive erasure coding, closed-loop control, anytime search, network reliability, model mismatch}
}
Document
Alignment Sets for Sensor Fusion Against Temporal Misalignment
Abstract
Sensor fusion algorithms combine data from multiple sensors to produce more accurate and reliable results. However, temporal misalignment between sensors, caused by factors such as clock drift, jitter or networking delays, can significantly degrade fusion quality. Prior work on modeling temporal misalignment in sensor fusion algorithms assumes that in the ideal case all samples should be aligned with the same reference time point. We show that this assumption limits its applicability when samples are intentionally taken at different time points, e.g., when a single sensor is sampled multiple times or when sensors operate at different frequencies.
In this paper, we introduce alignment sets, which allow system designers to explicitly specify the intended alignment between samples. This flexibility enables more precise temporal misalignment measures that better reflect the actual requirements of sensor fusion scenarios. We prove that alignment sets generalize the prior definitions of temporal misalignment of sensor fusion algorithms. We also provide an evaluation on a camera-LiDAR fusion pipeline for 3D object detection, showing that alignment sets provide more accurate misalignment measures and robustness estimates.
Cite as
Daniel Kuhse, Mario Günzel, Harun Teper, Lars Willemsen, Georg von der Brüggen, and Jian-Jia Chen. Alignment Sets for Sensor Fusion Against Temporal Misalignment. In 38th European Conference on Real-Time Systems (ECRTS 2026). Leibniz International Proceedings in Informatics (LIPIcs), Volume 375, pp. 8:1-8:24, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2026)
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@InProceedings{kuhse_et_al:LIPIcs.ECRTS.2026.8,
author = {Kuhse, Daniel and G\"{u}nzel, Mario and Teper, Harun and Willemsen, Lars and von der Br\"{u}ggen, Georg and Chen, Jian-Jia},
title = {{Alignment Sets for Sensor Fusion Against Temporal Misalignment}},
booktitle = {38th European Conference on Real-Time Systems (ECRTS 2026)},
pages = {8:1--8:24},
series = {Leibniz International Proceedings in Informatics (LIPIcs)},
ISBN = {978-3-95977-429-1},
ISSN = {1868-8969},
year = {2026},
volume = {375},
editor = {Kritikakou, Angeliki},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2026.8},
URN = {urn:nbn:de:0030-drops-266004},
doi = {10.4230/LIPIcs.ECRTS.2026.8},
annote = {Keywords: Sensor Fusion, Temporal Misalignment, Robustness, Timing Analysis}
}
Document
Randomizing Parallel Real-Time Tasks: A Scheduler-Oblivious Mechanism to Harness Security
Abstract
Periodic parallel task models, such as Directed Acyclic Graph (DAG), offer significant potential for modeling safety-critical real-time applications, but can introduce security vulnerabilities on multicore platforms. The deterministic schedules of periodic real-time tasks can be exploited through schedule-based side-channel attacks - causing missed deadlines or leaking sensitive information. Schedule randomization can address this vulnerability, yet existing work targets sequential tasks and lacks models that incorporate security for parallel workloads while meeting the real-time constraints. Furthermore, no widely accepted metric quantitatively measures the security gained from randomization against different attacker classes.
This paper proposes Controlled DAG Randomization (CDR), a scheduler-oblivious framework that randomizes the schedule of periodic real-time DAG tasks while preserving hard deadline guarantees. Each DAG is transformed into an Augmented DAG (ADAG) via two mechanisms: dependency augmentation, which adds edges to constrain concurrency, and temporal augmentation, which inserts additional vertices/subtasks that introduce random delays. At runtime, two algorithms randomize the structure of each released instance of the DAG: one adds random precedence edges, and the other assigns randomized execution budgets to the augmented subtasks of the ADAG - both while maintaining schedulability. Two attacker-aware metrics, System Threat and Task Distribution Entropy, are proposed, targeting intrusive and observation-based attackers, respectively. Extensive simulations on single- and multi-task systems show significant vulnerability reductions. We also observe that increased resources do not always strengthen security and can diminish randomization effectiveness, highlighting the need for carefully designed schedules to realize real security benefits.
Cite as
Xiuqi Zhang and Risat Mahmud Pathan. Randomizing Parallel Real-Time Tasks: A Scheduler-Oblivious Mechanism to Harness Security. In 38th European Conference on Real-Time Systems (ECRTS 2026). Leibniz International Proceedings in Informatics (LIPIcs), Volume 375, pp. 9:1-9:25, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2026)
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@InProceedings{zhang_et_al:LIPIcs.ECRTS.2026.9,
author = {Zhang, Xiuqi and Pathan, Risat Mahmud},
title = {{Randomizing Parallel Real-Time Tasks: A Scheduler-Oblivious Mechanism to Harness Security}},
booktitle = {38th European Conference on Real-Time Systems (ECRTS 2026)},
pages = {9:1--9:25},
series = {Leibniz International Proceedings in Informatics (LIPIcs)},
ISBN = {978-3-95977-429-1},
ISSN = {1868-8969},
year = {2026},
volume = {375},
editor = {Kritikakou, Angeliki},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2026.9},
URN = {urn:nbn:de:0030-drops-266014},
doi = {10.4230/LIPIcs.ECRTS.2026.9},
annote = {Keywords: Real-time systems, DAG scheduling, side-channel defense}
}
Document
DART: A Real-Time Address-Randomization Defense with Predictable Timing
Abstract
Embedded and real-time systems are increasingly connected and deployed in safety and mission-critical environments, making them a persistent target for attacks capable of compromising industrial control systems and other embedded devices. At the same time, these devices often have strict real-time requirements that require predictable worst-case performance. However, many strong and widely deployed software-security defenses are designed and evaluated with respect to average-case performance, a more important metric in enterprise systems. The worst-case performance of such defenses is not well understood and indeed such defenses are less commonly deployed in embedded systems. In particular, one class of commonly deployed defenses in enterprise systems is code randomization, which protects a system by altering the layout of the virtual address space so that attackers cannot easily target specific parts of a vulnerable application, but randomization is often seen as fundamentally counter to real-time predictability.
This paper presents DART, a real-time address randomization defense with page-level randomization. DART randomizes code in the virtual address space at page-level granularity under placement constraints that move cache behavior from a runtime OS-allocator property to a statically encoded binary property, allowing for timing analysis. An analysis of DART’s timing behavior on a real-time testbed demonstrates how the design makes layout-induced timing variance bounded and characterizable across the space of layouts produced, supporting predictable execution-time analysis. The resulting layout search space is then analyzed, and a closed-form expression for the randomization entropy induced by DART is derived. Evaluation results across TACLeBench binaries show increased combinatorial entropy with modest numbers of virtual memory pages per cache color, providing a suitable defense that outperforms traditional virtual-memory protections for attacks such as partial-pointer overwriting or more broadly control-flow hijacking.
Cite as
Patrick Dobranowski, Owen Rice, Ryan Burrow, Nathan Burow, and Bryan C. Ward. DART: A Real-Time Address-Randomization Defense with Predictable Timing. In 38th European Conference on Real-Time Systems (ECRTS 2026). Leibniz International Proceedings in Informatics (LIPIcs), Volume 375, pp. 10:1-10:26, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2026)
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@InProceedings{dobranowski_et_al:LIPIcs.ECRTS.2026.10,
author = {Dobranowski, Patrick and Rice, Owen and Burrow, Ryan and Burow, Nathan and Ward, Bryan C.},
title = {{DART: A Real-Time Address-Randomization Defense with Predictable Timing}},
booktitle = {38th European Conference on Real-Time Systems (ECRTS 2026)},
pages = {10:1--10:26},
series = {Leibniz International Proceedings in Informatics (LIPIcs)},
ISBN = {978-3-95977-429-1},
ISSN = {1868-8969},
year = {2026},
volume = {375},
editor = {Kritikakou, Angeliki},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2026.10},
URN = {urn:nbn:de:0030-drops-266021},
doi = {10.4230/LIPIcs.ECRTS.2026.10},
annote = {Keywords: real-time systems, address-space layout randomization, code randomization, worst-case execution time, cache coloring, embedded systems security}
}
Document
On DoS Attacks Exploiting Input Representativeness in Mixed-Criticality Systems
Abstract
In order to satisfy power, area and cost constraints, modern Cyber-Physical Systems (CPSs) often consolidate tasks with vastly different assurance requirements onto a shared platform. Mixed-Criticality Systems (MCSs) enable this consolidation while maintaining timing guarantees on complex hardware through probabilistic timing analysis. Among these techniques, Measurement-Based Probabilistic Timing Analysis (MBPTA) has gained popularity in recent years; it works by deriving Worst-Case Execution Time (WCET) estimates from input samples collected at design time. The impossibility of fully covering tasks' input space during MBPTA can pave the way for Denial-of-Service (DoS) attacks: adversaries can, for example, craft data-oriented and sensor spoofing attacks that force execution along unobserved paths, inducing WCET overruns and deadline violations. This work demonstrates that temporal DoS attacks exploiting insufficient input representativeness pose a credible threat to MCSs, showing substantial impact on availability and criticality mode transitions through comprehensive simulations. Next, rather than pursuing unattainable perfect input coverage at design time, we investigate runtime detection via monitoring of execution-time distributions and propose a novel Goodness-of-Fit-based detection mechanism. Our detection approach exhibits improved accuracy and reduced variance compared to existing iid-based methods, offering more stable performance across heterogeneous workloads. The trade-off is higher detection latency, necessitating careful analysis of system-specific tolerance windows before deployment. Evaluation demonstrates both the practical threat posed by timing-based attacks and the viability of distribution-based anomaly detection, while acknowledging that synthetic evaluation cannot alone validate real-world applicability.
Cite as
Nicolas Benatti, Federico Reghenzani, and Vittorio Zaccaria. On DoS Attacks Exploiting Input Representativeness in Mixed-Criticality Systems. In 38th European Conference on Real-Time Systems (ECRTS 2026). Leibniz International Proceedings in Informatics (LIPIcs), Volume 375, pp. 11:1-11:25, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2026)
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@InProceedings{benatti_et_al:LIPIcs.ECRTS.2026.11,
author = {Benatti, Nicolas and Reghenzani, Federico and Zaccaria, Vittorio},
title = {{On DoS Attacks Exploiting Input Representativeness in Mixed-Criticality Systems}},
booktitle = {38th European Conference on Real-Time Systems (ECRTS 2026)},
pages = {11:1--11:25},
series = {Leibniz International Proceedings in Informatics (LIPIcs)},
ISBN = {978-3-95977-429-1},
ISSN = {1868-8969},
year = {2026},
volume = {375},
editor = {Kritikakou, Angeliki},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2026.11},
URN = {urn:nbn:de:0030-drops-266039},
doi = {10.4230/LIPIcs.ECRTS.2026.11},
annote = {Keywords: Cyber-physical systems, mixed-criticality systems, pWCET, denial-of-service, spoofing, data-oriented attack}
}
Document
Schedule-Based Attack Against TSN TAS with Frame Preemption
Abstract
Time-Sensitive Networking (TSN) achieves deterministic communication using mechanisms like Time-Aware Shaping, which manages the timing of network traffic streams using a Gate Control List (GCL). The GCL operates according to a cyclic schedule by opening and closing gates for priority (egress) queues in out-bound ports. However, the cyclic schedule in the GCL introduces potential security vulnerabilities to schedule-based attacks. This type of attack exploits TSN’s deterministic schedules to manipulate traffic flow and can impact availability and safety. Traditional intrusion detection systems (IDS) are commonly employed in TSN to detect malicious activities by monitoring traffic patterns and bandwidth usage. However, schedule-based attacks can align malicious packets with legitimate traffic, making the attack more stealthy and harder to detect by rate-based IDS. This paper presents a novel schedule-based attack that synchronizes malicious traffic to exploit predictability in TSN’s GCL schedule. This attack causes an adversarial blocking in which low-priority traffic delays higher-priority traffic without being detected using a rate-based IDS. We demonstrate the feasibility and impact of this schedule-based attack on TSN with off-the-shelf hardware.
Cite as
Omolade Ikumapayi, Vijay Banerjee, Sena Hounsinou, and Gedare Bloom. Schedule-Based Attack Against TSN TAS with Frame Preemption. In 38th European Conference on Real-Time Systems (ECRTS 2026). Leibniz International Proceedings in Informatics (LIPIcs), Volume 375, pp. 12:1-12:23, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2026)
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@InProceedings{ikumapayi_et_al:LIPIcs.ECRTS.2026.12,
author = {Ikumapayi, Omolade and Banerjee, Vijay and Hounsinou, Sena and Bloom, Gedare},
title = {{Schedule-Based Attack Against TSN TAS with Frame Preemption}},
booktitle = {38th European Conference on Real-Time Systems (ECRTS 2026)},
pages = {12:1--12:23},
series = {Leibniz International Proceedings in Informatics (LIPIcs)},
ISBN = {978-3-95977-429-1},
ISSN = {1868-8969},
year = {2026},
volume = {375},
editor = {Kritikakou, Angeliki},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2026.12},
URN = {urn:nbn:de:0030-drops-266042},
doi = {10.4230/LIPIcs.ECRTS.2026.12},
annote = {Keywords: schedule-based attack, time-sensitive networking, real-time system, adversarial blocking}
}
Document
CacheFlow: Using Maximum Flow to Bound Cache-Based Preemption Delays
Abstract
Cache-related preemption delay (CRPD) analysis bounds the additional execution time caused by cache evictions during preemptions. Tightly bounding CRPDs is challenging as there are many possible preemption patterns that can occur at runtime, and thus there has been continuous work over three decades to refine these bounds. This paper presents CacheFlow, a framework that formulates total CRPD as a maximum-flow problem. In the flow network, nodes and edge capacities can be constructed to model certain eviction patterns that can occur. Therefore, by (safely) removing nodes or edges, or reducing edge capacities, tighter CRPD bounds can be derived. This is demonstrated with different CacheFlow refinements, some of which include insights from prior analyses, as well as a refinement for simply periodic systems. An iterative max-flow formulation is also described to more efficiently integrate the max-flow solving in the context of standard fixed-priority response-time analysis. Experiments on synthetic task systems demonstrate significant schedulability improvements across a range of system configurations, while also having reasonable solving times.
Cite as
Tiancheng He and Bryan C. Ward. CacheFlow: Using Maximum Flow to Bound Cache-Based Preemption Delays. In 38th European Conference on Real-Time Systems (ECRTS 2026). Leibniz International Proceedings in Informatics (LIPIcs), Volume 375, pp. 13:1-13:22, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2026)
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@InProceedings{he_et_al:LIPIcs.ECRTS.2026.13,
author = {He, Tiancheng and Ward, Bryan C.},
title = {{CacheFlow: Using Maximum Flow to Bound Cache-Based Preemption Delays}},
booktitle = {38th European Conference on Real-Time Systems (ECRTS 2026)},
pages = {13:1--13:22},
series = {Leibniz International Proceedings in Informatics (LIPIcs)},
ISBN = {978-3-95977-429-1},
ISSN = {1868-8969},
year = {2026},
volume = {375},
editor = {Kritikakou, Angeliki},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2026.13},
URN = {urn:nbn:de:0030-drops-266058},
doi = {10.4230/LIPIcs.ECRTS.2026.13},
annote = {Keywords: Cache-related Preemption Delay, Real-Time Systems, Maximum Flow}
}
Document
WCET Analysis of HLS-Generated Processors Using Abstract Interpretation
Abstract
Deriving sound and precise timing models remains one of the main obstacles to static Worst-Case Execution Time (WCET) analysis. Modern processors exhibit diverse and evolving microarchitectures, making manual construction of timing models labor-intensive, error-prone, and difficult to adapt across processor variants. High-Level Synthesis (HLS) enables rapid customization of processor cores and architectural exploration, offering an opportunity to automate not only hardware generation but also the derivation of associated timing models.
This paper presents an automated WCET analysis for HLS-generated processors based on abstract interpretation. We exploit the internal Gated-SSA representation of the HLS flow to automatically extract an abstract timing model capturing speculation and stall mechanisms. WCET estimation at the basic block level is then formulated as an exploration of abstract microarchitectural states within a basic block.
The approach safely accounts for timing anomalies, while remaining scalable thanks to an efficient state-merging strategy. Integrated into the Heptane WCET tool and evaluated on Mälardalen benchmarks and a RISC-V, the method achieves the same tightness as a handcrafted timing model, while improving over a previously proposed automated approach.
Cite as
Thomas Feuilletin, Dylan Leothaud, Simon Rokicki, Steven Derrien, and Isabelle Puaut. WCET Analysis of HLS-Generated Processors Using Abstract Interpretation. In 38th European Conference on Real-Time Systems (ECRTS 2026). Leibniz International Proceedings in Informatics (LIPIcs), Volume 375, pp. 14:1-14:19, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2026)
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@InProceedings{feuilletin_et_al:LIPIcs.ECRTS.2026.14,
author = {Feuilletin, Thomas and Leothaud, Dylan and Rokicki, Simon and Derrien, Steven and Puaut, Isabelle},
title = {{WCET Analysis of HLS-Generated Processors Using Abstract Interpretation}},
booktitle = {38th European Conference on Real-Time Systems (ECRTS 2026)},
pages = {14:1--14:19},
series = {Leibniz International Proceedings in Informatics (LIPIcs)},
ISBN = {978-3-95977-429-1},
ISSN = {1868-8969},
year = {2026},
volume = {375},
editor = {Kritikakou, Angeliki},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2026.14},
URN = {urn:nbn:de:0030-drops-266069},
doi = {10.4230/LIPIcs.ECRTS.2026.14},
annote = {Keywords: Static Analysis, Worst-Case Execution Time, High-Level Synthesis}
}
Document
BRUMM: A Case for Predictable Memory Reclamation
Abstract
Edge data centers process latency-sensitive workloads of nearby Internet-of-Things devices. These security-critical, multi-tenant environments are equipped with comparatively limited compute resources. Consequently, resource management must be fast and predictable even in the presence of malicious tenants because there is no surplus of resources to compensate for performance attacks. In particular, there is a need to constrain the time it takes to reclaim memory from applications. Existing accounting mechanisms in operating systems focus on limiting memory or scheduling-time usage; they provide no guarantees about the latency of resource reclamation, which can vary greatly and is a potential vector for performance attacks.
To solve this standing issue, we introduce BRUMM (Bounded Reclamation of User-space Memory Mappings): This accounting-driven mechanism predicts and tracks how long it will take to reclaim memory allocated to applications, enforcing an upper limit via a configurable latency budget. As a case study, we extended the L4Re microkernel to add a quota object for reclamation latency and enforce its limit. Our evaluation demonstrates that this implementation of BRUMM achieves a consistent overestimation of reclamation latency, staying within the same order of magnitude to real, measured latencies. The implementation only shows modest performance overhead on kernel operations, ranging from 2.4% overhead for simple system calls to 28% in synthetic worst-case scenarios. BRUMM makes reclamation latency a first-class resource that can be accounted for, thereby improving isolation and reliability in edge clouds.
Cite as
Viktor Reusch, Michael Roitzsch, and Horst Schirmeier. BRUMM: A Case for Predictable Memory Reclamation. In 38th European Conference on Real-Time Systems (ECRTS 2026). Leibniz International Proceedings in Informatics (LIPIcs), Volume 375, pp. 15:1-15:24, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2026)
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@InProceedings{reusch_et_al:LIPIcs.ECRTS.2026.15,
author = {Reusch, Viktor and Roitzsch, Michael and Schirmeier, Horst},
title = {{BRUMM: A Case for Predictable Memory Reclamation}},
booktitle = {38th European Conference on Real-Time Systems (ECRTS 2026)},
pages = {15:1--15:24},
series = {Leibniz International Proceedings in Informatics (LIPIcs)},
ISBN = {978-3-95977-429-1},
ISSN = {1868-8969},
year = {2026},
volume = {375},
editor = {Kritikakou, Angeliki},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2026.15},
URN = {urn:nbn:de:0030-drops-266072},
doi = {10.4230/LIPIcs.ECRTS.2026.15},
annote = {Keywords: Resource Reclamation, Main Memory, Accounting, Operating System, Microkernel, Capability, L4Re}
}
Document
DySM: Dynamic Scaling of GPU Streaming Multiprocessor in Spatially Shared Real-Time Embedded GPU Systems
Abstract
Many of today’s real-time embedded systems are increasingly relying on GPUs for AI-related computing. However, existing GPU scheduling solutions for spatially shared GPU systems are still mostly open-loop and rely on worst-case execution time (WCET) estimation for offline schedulability analysis, which cannot adapt to online workload variations. Although adaptive scheduling has been proposed to handle runtime execution time variations, prior approaches target either CPU or time-slicing GPUs, where only one task can execute on the GPU within a time slice. In contrast, spatial sharing enables concurrent kernel execution via Streaming Multiprocessor (SM) partitioning, allowing better GPU resource utilization. Therefore, new adaptive solutions must be designed for spatially shared GPU systems.
In this paper, we propose DySM, a closed-loop response time control algorithm for spatially shared GPUs in soft real-time systems. In face of runtime workload variations, DySM leverages dynamic SM scaling to control task response times with low runtime overhead. To model GPU resource contention among tasks, we analytically derive a multi-input-multi-output (MIMO) system model that captures the impact of SM scaling on the response times of different tasks. Based on this model, DySM is designed using feedback control theory for guaranteed system stability and control accuracy. Experimental results on an Nvidia GPU testbed demonstrate that DySM outperforms state-of-the-art solutions by providing runtime real-time guarantees. Compared to the best-performing baseline, DySM can reduce the deadline miss ratio by up to 90.93%.
Cite as
Srinivasan Subramaniyan and Xiaorui Wang. DySM: Dynamic Scaling of GPU Streaming Multiprocessor in Spatially Shared Real-Time Embedded GPU Systems. In 38th European Conference on Real-Time Systems (ECRTS 2026). Leibniz International Proceedings in Informatics (LIPIcs), Volume 375, pp. 16:1-16:24, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2026)
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@InProceedings{subramaniyan_et_al:LIPIcs.ECRTS.2026.16,
author = {Subramaniyan, Srinivasan and Wang, Xiaorui},
title = {{DySM: Dynamic Scaling of GPU Streaming Multiprocessor in Spatially Shared Real-Time Embedded GPU Systems}},
booktitle = {38th European Conference on Real-Time Systems (ECRTS 2026)},
pages = {16:1--16:24},
series = {Leibniz International Proceedings in Informatics (LIPIcs)},
ISBN = {978-3-95977-429-1},
ISSN = {1868-8969},
year = {2026},
volume = {375},
editor = {Kritikakou, Angeliki},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2026.16},
URN = {urn:nbn:de:0030-drops-266080},
doi = {10.4230/LIPIcs.ECRTS.2026.16},
annote = {Keywords: Real-time systems, GPU scheduling, response time ratio control, SM scaling, and feedback control}
}
Document
Uncertainty-Aware Resource Allocation for Multi-Path Programs with In-Kernel Predictions
Abstract
Predictable timing on multicore systems requires careful management of shared resources such as the last-level cache and memory bandwidth. This paper presents MPORA, an uncertainty-aware dynamic resource allocation framework for multi-path, input-dependent real-time tasks on multicore platforms. MPORA models each job as a discrete-time dynamical system that captures execution dynamics and resource-dependent performance indicators. At runtime, MPORA monitors job execution states and predicts short-term instruction rates and remaining execution times under candidate allocations using predictive models trained offline. It then solves a receding-horizon optimization problem to compute resource allocations that maximize system-wide progress while meeting job deadlines. To address prediction uncertainty, MPORA integrates weighted conformal prediction into the optimization formulation, enabling uncertainty-aware deadline constraints. We implement MPORA as a Linux kernel module with microsecond-scale inference overhead. Experimental results on SPEC CPU benchmarks show that MPORA delivers accurate predictions under unseen inputs and distribution shifts with low overhead, while improving schedulability and response times over existing methods.
Cite as
Abigail Eisenklam, Carlos A. Montenegro G., Xian Wang, Yifan Cai, Robert Gifford, Linh Thi Xuan Phan, and Ricardo G. Sanfelice. Uncertainty-Aware Resource Allocation for Multi-Path Programs with In-Kernel Predictions. In 38th European Conference on Real-Time Systems (ECRTS 2026). Leibniz International Proceedings in Informatics (LIPIcs), Volume 375, pp. 17:1-17:26, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2026)
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@InProceedings{eisenklam_et_al:LIPIcs.ECRTS.2026.17,
author = {Eisenklam, Abigail and Montenegro G., Carlos A. and Wang, Xian and Cai, Yifan and Gifford, Robert and Phan, Linh Thi Xuan and Sanfelice, Ricardo G.},
title = {{Uncertainty-Aware Resource Allocation for Multi-Path Programs with In-Kernel Predictions}},
booktitle = {38th European Conference on Real-Time Systems (ECRTS 2026)},
pages = {17:1--17:26},
series = {Leibniz International Proceedings in Informatics (LIPIcs)},
ISBN = {978-3-95977-429-1},
ISSN = {1868-8969},
year = {2026},
volume = {375},
editor = {Kritikakou, Angeliki},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2026.17},
URN = {urn:nbn:de:0030-drops-266095},
doi = {10.4230/LIPIcs.ECRTS.2026.17},
annote = {Keywords: multicore, resource allocation, optimal control, learning, multi-path programs}
}
Document
DAAT‑MCS: A Framework to Deploy, Analyse, and Auto‑Tune Interference Mitigation Techniques in Mixed‑Criticality Systems
Abstract
The consolidation of workloads with different criticality levels onto shared multi-core platforms is widely adopted to meet stringent SWaP-C constraints, giving rise to mixed-criticality systems. This consolidation is often enabled by static partitioning hypervisors, which provide strong spatial isolation via static assignment of resources such as cores, memory regions, and devices. However, temporal isolation remains challenging because key microarchitectural resources (e.g., the last-level cache and the memory subsystem) are still shared and can induce contention-driven slowdowns and loss of predictability. Cache coloring and related mitigation techniques can reduce this interference, but their configuration is still typically performed offline via manual profiling and trial-and-error, which is time-consuming, error-prone, and highly workload- and platform-dependent. The remaining gap is therefore not the lack of mitigation mechanisms, but the lack of a systematic way to derive a deployable partition for a given workload mix under explicit timing requirements.
This paper presents DAAT-MCS, an end-to-end framework that automates cache-color assignment for static partitioning hypervisors. It consists of two components: (i) the DAAT-MCS profiler, which systematically deploys and measures a bounded set of cache partitions on real hardware to quantify interference effects in mixed-criticality consolidations; and (ii) the DAAT-MCS tuner, which uses these measurements to automatically derive the set of system-wide cache partitions that satisfy user-defined per-core performance-degradation tolerances. Together, these components turn cache-color tuning from ad-hoc trial-and-error into a repeatable, measurement-driven integration step with explicit acceptance criteria. We evaluate DAAT-MCS on an ARMv8-A Xilinx UltraScale+ ZCU104 platform across 264 workload combinations and 7 cache-partitioning configurations (1848 setups, >60 h of automated profiling). For 28 tuner settings on a subset of 154 out of the 1848 consolidations (one memory-intensive benchmark co-scheduled with 22 co-runners across 7 cache partitions), totaling 4,312 tuner runs, DAAT-MCS finds no acceptable cache partition in 84.53% of cases and returns at least one deployable configuration in the remaining 15.47%, reducing the integration search space whenever feasibility exists and avoiding manual trial-and-error. All artifacts, including code, raw traces, and reproduction infrastructure, are publicly available.
Cite as
Diogo Costa and Sandro Pinto. DAAT‑MCS: A Framework to Deploy, Analyse, and Auto‑Tune Interference Mitigation Techniques in Mixed‑Criticality Systems. In 38th European Conference on Real-Time Systems (ECRTS 2026). Leibniz International Proceedings in Informatics (LIPIcs), Volume 375, pp. 18:1-18:26, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2026)
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@InProceedings{costa_et_al:LIPIcs.ECRTS.2026.18,
author = {Costa, Diogo and Pinto, Sandro},
title = {{DAAT‑MCS: A Framework to Deploy, Analyse, and Auto‑Tune Interference Mitigation Techniques in Mixed‑Criticality Systems}},
booktitle = {38th European Conference on Real-Time Systems (ECRTS 2026)},
pages = {18:1--18:26},
series = {Leibniz International Proceedings in Informatics (LIPIcs)},
ISBN = {978-3-95977-429-1},
ISSN = {1868-8969},
year = {2026},
volume = {375},
editor = {Kritikakou, Angeliki},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2026.18},
URN = {urn:nbn:de:0030-drops-266108},
doi = {10.4230/LIPIcs.ECRTS.2026.18},
annote = {Keywords: Auto-Tune, Cache Coloring, Interference, Contention, Mixed-Criticality Systems, Virtualization}
}
Document
From Timing Budgets to WCETs: Robust SIL- and BSW-Aware Clustering and Allocation for Iterative Automotive Software Development
Abstract
Automotive ECUs integrate thousands of AUTOSAR runnables, substantial Basic Software (BSW), and heterogeneous multicore hardware. In iterative software-defined vehicle development, engineers must repeatedly revisit designs while maintaining stable runnable clustering and core allocations, which are expensive structural decisions. Beyond timing, Safety Integrity Levels (SILs), BSW overheads, and per-core memory strongly constrain these decisions, yet are rarely modeled jointly. This paper addresses these challenges through a chain-based analysis model that treats SIL constraints and BSW costs as first-class citizens, as well as an integrated toolchain that constructs job-level data-age constraints, forms SIL-compliant clusters, synthesizes multirate tasks, and maps application and BSW tasks to heterogeneous multicore platforms while checking timing and memory feasibility.
A case study based on a real-world motion/drive controller from our industrial partner is described, which serves as the basis for our evaluation. The evaluations are conducted using synthetic systems that reflect the characteristics of the case study. Across 13,825 synthesized systems, SIL/BSW-aware clustering substantially reduces pessimism in analysis. In the industrial configuration, our approach yields a 7% decrease in utilization, demonstrating its practical value. A refinement study, which progressively replaces early budget assumptions with WCET samples, indicates that SIL/BSW-aware clustering preserves structural decisions better than less-informed variants under the same resampling setup.
Cite as
Tobias Denzinger, Matthias Becker, and Peter Ulbrich. From Timing Budgets to WCETs: Robust SIL- and BSW-Aware Clustering and Allocation for Iterative Automotive Software Development. In 38th European Conference on Real-Time Systems (ECRTS 2026). Leibniz International Proceedings in Informatics (LIPIcs), Volume 375, pp. 19:1-19:27, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2026)
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@InProceedings{denzinger_et_al:LIPIcs.ECRTS.2026.19,
author = {Denzinger, Tobias and Becker, Matthias and Ulbrich, Peter},
title = {{From Timing Budgets to WCETs: Robust SIL- and BSW-Aware Clustering and Allocation for Iterative Automotive Software Development}},
booktitle = {38th European Conference on Real-Time Systems (ECRTS 2026)},
pages = {19:1--19:27},
series = {Leibniz International Proceedings in Informatics (LIPIcs)},
ISBN = {978-3-95977-429-1},
ISSN = {1868-8969},
year = {2026},
volume = {375},
editor = {Kritikakou, Angeliki},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2026.19},
URN = {urn:nbn:de:0030-drops-266116},
doi = {10.4230/LIPIcs.ECRTS.2026.19},
annote = {Keywords: cause-effect chains, end-to-end latency constraints, automotive software, SIL, ASIL, AUTOSAR BSW, WCET refinement, timing analysis}
}
Document
Multi-Core Integration of Sporadic Events in Time-Triggered Systems
Abstract
Modern safety-critical systems often feature multi-core multi-SoC platforms and execute both periodic and sporadic workloads with real-time requirements. Periodic tasks benefit from a time-triggered (TT) approach, while sporadic events are best modeled by event-triggered (ET) tasks and scheduled using classical online mechanisms such as fixed-priority. Integrating TT and ET tasks in a multi-core environment has mainly been studied in fully partitioned solutions. However, for certain workloads, it may be beneficial to have a global scheduling approach for ET tasks. In this paper, we extend the current state-of-the-art in Response-Time Analysis (RTA) and Real-Time Calculus (RTC) to analyze the schedulability of sporadic ET tasks in a homogeneous multi-core TT system. We generalize previous promising results integrating TT and ET tasks using affine envelopes to homogeneous multi-core systems. While our method can be applied to any TT schedule generation mechanism, we also present a concrete schedule synthesis method based on a variant of the Least-Laxity First scheduling approach. We demonstrate the performance of our approach, in terms of both schedulability and runtime, through real-world and synthetic experiments inspired by real workloads. We note that our affine-envelope-based interference bound and the generalized burst limiting constraint (BLC) are also independent of the concrete TT synthesis algorithm and of the underlying timing analysis method (RTA or RTC). This modularity allows the framework to be combined with alternative schedulability analyses or TT schedule generation techniques, while preserving the demonstrated gains in schedulability and scalability for mixed TT and ET workloads on homogeneous multi-core platforms.
Cite as
Anaïs Finzi and Silviu S. Craciunas. Multi-Core Integration of Sporadic Events in Time-Triggered Systems. In 38th European Conference on Real-Time Systems (ECRTS 2026). Leibniz International Proceedings in Informatics (LIPIcs), Volume 375, pp. 20:1-20:23, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2026)
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@InProceedings{finzi_et_al:LIPIcs.ECRTS.2026.20,
author = {Finzi, Ana\"{i}s and Craciunas, Silviu S.},
title = {{Multi-Core Integration of Sporadic Events in Time-Triggered Systems}},
booktitle = {38th European Conference on Real-Time Systems (ECRTS 2026)},
pages = {20:1--20:23},
series = {Leibniz International Proceedings in Informatics (LIPIcs)},
ISBN = {978-3-95977-429-1},
ISSN = {1868-8969},
year = {2026},
volume = {375},
editor = {Kritikakou, Angeliki},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2026.20},
URN = {urn:nbn:de:0030-drops-266126},
doi = {10.4230/LIPIcs.ECRTS.2026.20},
annote = {Keywords: time-triggered (TT), event-triggered (ET), scheduling, real-time, real-time calculus, response-time analysis}
}
Document
Semi-Clairvoyant Scheduling for Jobs with Multiple Criticalities
Abstract
This paper considers scheduling jobs semi-clairvoyantly in mixed-criticality systems. In the semi-clairvoyant model, unlike the non-clairvoyant model, we know the WCET mode of the job at job arrival. Prior work has only considered this model for dual criticality jobs. We consider this problem for an arbitrary number of criticalities. We prove that there exist semi-clairvoyant schedulers that guarantee schedulability with speedup (2^m-1)/2^{m-1} for systems with m criticality levels. In addition, we prove that this bound is tight by providing a job set construction that requires this speed for any semi-clairvoyant scheduler. Finally we provide a linear programming formulation that optimally schedules the semi-clairvoyant system of jobs. The number of variables and constraints is polynomial in the number of jobs, but exponential in the number of criticalities.
Cite as
Kunal Agrawal, Tung Duc Thai, and Jinhao Zhao. Semi-Clairvoyant Scheduling for Jobs with Multiple Criticalities. In 38th European Conference on Real-Time Systems (ECRTS 2026). Leibniz International Proceedings in Informatics (LIPIcs), Volume 375, pp. 21:1-21:23, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2026)
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@InProceedings{agrawal_et_al:LIPIcs.ECRTS.2026.21,
author = {Agrawal, Kunal and Thai, Tung Duc and Zhao, Jinhao},
title = {{Semi-Clairvoyant Scheduling for Jobs with Multiple Criticalities}},
booktitle = {38th European Conference on Real-Time Systems (ECRTS 2026)},
pages = {21:1--21:23},
series = {Leibniz International Proceedings in Informatics (LIPIcs)},
ISBN = {978-3-95977-429-1},
ISSN = {1868-8969},
year = {2026},
volume = {375},
editor = {Kritikakou, Angeliki},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2026.21},
URN = {urn:nbn:de:0030-drops-266130},
doi = {10.4230/LIPIcs.ECRTS.2026.21},
annote = {Keywords: mixed-criticality, semi-clairvoyance, schedulers, linear programming}
}
Document
PREEMPT-FaaS: Taming Orchestration Times in Latency-Sensitive Serverless Environments
Abstract
The orchestration of application instances is critical for the efficient management of cloud computing platforms. Specifically, the serverless paradigm automates container spawning and de-spawning based on actual load, mitigating inefficiencies, such as over- and under-provisioning, that might compromise Service Level Objectives (SLOs). This dynamic behavior introduces significant challenges concerning initialization and termination latencies, which are exacerbated when enforcing real-time requirements in mixed-criticality systems. The existing literature already addresses key issues, such as reducing cold-start times and assuring real-time performance to deployed instances. However, container orchestration times remain an overlooked factor that can severely affect instance startup times, especially when the orchestrator is subject to intense workloads. In this paper, we present PREEMPT-FaaS, an orchestration controller that, unlike commonly adopted controllers, adopts a fixed-priority preemptive scheduling of requests to guarantee reduced orchestration times to high-priority and highly critical instances. We implemented PREEMPT-FaaS as a Rust custom controller for Kubernetes (K8s), along with a patch for Knative, a popular serverless platform built upon K8s. We perform an extensive experimental campaign of PREEMPT-FaaS, including the serving of AI workloads, such as, recurring neural networks and video analytics, showing up to ∼6× reduction of orchestration times under high load and improving end-to-end cold-start times of critical instances, with a consequent reduction of service-level latencies (up to ∼2 s reduction under stress at the 95th percentile).
Cite as
Marcello Cinque, Luigi De Simone, Raffaele Della Corte, and Stefano Toscano. PREEMPT-FaaS: Taming Orchestration Times in Latency-Sensitive Serverless Environments. In 38th European Conference on Real-Time Systems (ECRTS 2026). Leibniz International Proceedings in Informatics (LIPIcs), Volume 375, pp. 22:1-22:25, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2026)
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@InProceedings{cinque_et_al:LIPIcs.ECRTS.2026.22,
author = {Cinque, Marcello and De Simone, Luigi and Della Corte, Raffaele and Toscano, Stefano},
title = {{PREEMPT-FaaS: Taming Orchestration Times in Latency-Sensitive Serverless Environments}},
booktitle = {38th European Conference on Real-Time Systems (ECRTS 2026)},
pages = {22:1--22:25},
series = {Leibniz International Proceedings in Informatics (LIPIcs)},
ISBN = {978-3-95977-429-1},
ISSN = {1868-8969},
year = {2026},
volume = {375},
editor = {Kritikakou, Angeliki},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2026.22},
URN = {urn:nbn:de:0030-drops-266155},
doi = {10.4230/LIPIcs.ECRTS.2026.22},
annote = {Keywords: Edge-Cloud, Orchestration, Containers, Mixed-Criticality, Kubernetes}
}
Document
HyperSSE: Cross-Domain Static Analysis of Partitioned Real-Time Hypervisor Systems
Abstract
Timing analysis for embedded real-time systems is crucial to guarantee the correct behavior and to calculate the Worst-Case Response Time (WCRT) of safety-critical applications. With the increasing requirements of such systems in automotive, industrial or avionic industries, consolidation of multiple real-time and general-purpose operating systems on a single high-performance Multiprocessor System-on-Chip (MPSoC) platform using Static Partitioning Hypervisors (SPHs) is becoming more prevalent. Although the strong separation is well suited to reduce interference between isolated domains in such mixed-criticality systems, cross-domain interactions must still be considered in real-time analysis. Previous work has focused on dynamic monitoring and enforcement of timing constraints in virtualized environments.
In this paper, we present HyperSSE, the first approach for the static analysis of cross-domain interactions in hypervisor-based real-time systems. By hierarchically combining existing domain-local static analyses, and synchronizing the control flow at cross-domain interactions, we enable control-flow-sensitive whole-platform analysis including multiple real-time domains. Using abstract task models, this approach can integrate a coarser analysis of general-purpose operating systems, accelerators, and coprocessors with the precise timing analysis. We demonstrate the applicability of HyperSSE in an automotive case study with mixed-criticality software stacks running on Xen in a static partitioning configuration. The resulting Hypervisor State Transition Graph (HSTG) exposes deep knowledge about the platform interactions, enabling cross-domain timing analysis with reduction of pessimistic WCRT calculations. Additionally, HyperSSE can be used for placement optimizations for better predictability, verification of critical interaction paths, and is the foundation for further platform-level analyses, such as analysis of implicit interactions through transparent resource sharing.
Cite as
Andreas Kässens, Mareike Burg, and Daniel Lohmann. HyperSSE: Cross-Domain Static Analysis of Partitioned Real-Time Hypervisor Systems. In 38th European Conference on Real-Time Systems (ECRTS 2026). Leibniz International Proceedings in Informatics (LIPIcs), Volume 375, pp. 23:1-23:27, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2026)
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@InProceedings{kassens_et_al:LIPIcs.ECRTS.2026.23,
author = {K\"{a}ssens, Andreas and Burg, Mareike and Lohmann, Daniel},
title = {{HyperSSE: Cross-Domain Static Analysis of Partitioned Real-Time Hypervisor Systems}},
booktitle = {38th European Conference on Real-Time Systems (ECRTS 2026)},
pages = {23:1--23:27},
series = {Leibniz International Proceedings in Informatics (LIPIcs)},
ISBN = {978-3-95977-429-1},
ISSN = {1868-8969},
year = {2026},
volume = {375},
editor = {Kritikakou, Angeliki},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2026.23},
URN = {urn:nbn:de:0030-drops-266165},
doi = {10.4230/LIPIcs.ECRTS.2026.23},
annote = {Keywords: Static Analysis, Hypervisor, Real-Time Operating System, Cross-Domain}
}