Volume
LIPIcs, Volume 298
36th Euromicro Conference on Real-Time Systems (ECRTS 2024)
-
Part of:
Series:
Leibniz International Proceedings in Informatics (LIPIcs)
Conference: Euromicro Conference on Real-Time Systems (ECRTS)
Event
ECRTS 2024, July 9-12, 2024, Lille, FranceEditor
Publication Details
- published at: 2024-07-04
- Publisher: Schloss Dagstuhl – Leibniz-Zentrum für Informatik
- ISBN: 978-3-95977-324-9
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Document
Complete Volume
LIPIcs, Volume 298, ECRTS 2024, Complete Volume
Abstract
LIPIcs, Volume 298, ECRTS 2024, Complete Volume
Cite as
36th Euromicro Conference on Real-Time Systems (ECRTS 2024). Leibniz International Proceedings in Informatics (LIPIcs), Volume 298, pp. 1-436, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2024)
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@Proceedings{pellizzoni:LIPIcs.ECRTS.2024,
title = {{LIPIcs, Volume 298, ECRTS 2024, Complete Volume}},
booktitle = {36th Euromicro Conference on Real-Time Systems (ECRTS 2024)},
pages = {1--436},
series = {Leibniz International Proceedings in Informatics (LIPIcs)},
ISBN = {978-3-95977-324-9},
ISSN = {1868-8969},
year = {2024},
volume = {298},
editor = {Pellizzoni, Rodolfo},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2024},
URN = {urn:nbn:de:0030-drops-203024},
doi = {10.4230/LIPIcs.ECRTS.2024},
annote = {Keywords: LIPIcs, Volume 298, ECRTS 2024, Complete Volume}
}
Document
Front Matter
Front Matter, Table of Contents, Preface, Conference Organization
Abstract
Front Matter, Table of Contents, Preface, Conference Organization
Cite as
36th Euromicro Conference on Real-Time Systems (ECRTS 2024). Leibniz International Proceedings in Informatics (LIPIcs), Volume 298, pp. 0:i-0:xiv, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2024)
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@InProceedings{pellizzoni:LIPIcs.ECRTS.2024.0,
author = {Pellizzoni, Rodolfo},
title = {{Front Matter, Table of Contents, Preface, Conference Organization}},
booktitle = {36th Euromicro Conference on Real-Time Systems (ECRTS 2024)},
pages = {0:i--0:xiv},
series = {Leibniz International Proceedings in Informatics (LIPIcs)},
ISBN = {978-3-95977-324-9},
ISSN = {1868-8969},
year = {2024},
volume = {298},
editor = {Pellizzoni, Rodolfo},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2024.0},
URN = {urn:nbn:de:0030-drops-203034},
doi = {10.4230/LIPIcs.ECRTS.2024.0},
annote = {Keywords: Front Matter, Table of Contents, Preface, Conference Organization}
}
Document
JuMP2start: Time-Aware Stop-Start Technology for a Software-Defined Vehicle System
Abstract
Software-defined vehicle (SDV) systems replace traditional ECU architectures with software tasks running on centralized multicore processors in automotive-grade PCs. However, PC boot delays to cold-start an integrated vehicle management system (VMS) are problematic for time-critical functions, which must process sensor and actuator data within specific time bounds.
To tackle this challenge, we present JuMP2start: a time-aware multicore stop-start approach for SDVs. JuMP2start leverages PC-class suspend-to-RAM techniques to capture a system snapshot when the vehicle is stopped. Upon restart, critical services are resumed-from-RAM within order of milliseconds compared to normal cold-start times. This work showcases how JuMP2start manages global suspension and resumption mechanisms for a state-of-the-art dual-domain vehicle management system comprising real-time OS (RTOS) and Linux SMP guests. JuMP2start models automotive tasks as continuable or restartable to ensure timing- and safety-critical function pipelines are reactively resumed with low latency, while discarding stale task state. Experiments with the VMS show that critical CAN traffic processing resumes within 500 milliseconds of waking the RTOS guest, and reaches steady-state throughput in under 7ms.
Cite as
Anam Farrukh and Richard West. JuMP2start: Time-Aware Stop-Start Technology for a Software-Defined Vehicle System. In 36th Euromicro Conference on Real-Time Systems (ECRTS 2024). Leibniz International Proceedings in Informatics (LIPIcs), Volume 298, pp. 1:1-1:27, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2024)
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@InProceedings{farrukh_et_al:LIPIcs.ECRTS.2024.1,
author = {Farrukh, Anam and West, Richard},
title = {{JuMP2start: Time-Aware Stop-Start Technology for a Software-Defined Vehicle System}},
booktitle = {36th Euromicro Conference on Real-Time Systems (ECRTS 2024)},
pages = {1:1--1:27},
series = {Leibniz International Proceedings in Informatics (LIPIcs)},
ISBN = {978-3-95977-324-9},
ISSN = {1868-8969},
year = {2024},
volume = {298},
editor = {Pellizzoni, Rodolfo},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2024.1},
URN = {urn:nbn:de:0030-drops-203046},
doi = {10.4230/LIPIcs.ECRTS.2024.1},
annote = {Keywords: Time-aware stop-start, Real-time power management, Suspend-to-RAM, Partitioning hypervisor, Vehicle management system, Vehicle-OS, Software-defined vehicles (SDV)}
}
Document
SlackCheck: A Linux Kernel Module to Verify Temporal Properties of a Task Schedule
Abstract
The Linux Kernel offers several scheduling classes. From SCHED_DEADLINE down to SCHED_FIFO, SCHED_RR and SCHED_OTHER, the scheduling classes can provide different responsiveness to very diverse user workloads. Still, Linux does not offer any mechanism to take some action upon the violation of temporal constraints at runtime. The lack of such a feature is also due to the difficulty of extending the established notion of deadline to workloads which are not releasing periodic/sporadic jobs.
Exploiting the notion of supply functions for any resource schedule, we implemented SlackCheck, a kernel module which is capable to verify at runtime if a given task is assigned a desired amount of resource or not. SlackCheck adds a constant-time check at every scheduling decision and leverages the recent availability of a Runtime Verification engine in the kernel.
Cite as
Michele Castrovilli and Enrico Bini. SlackCheck: A Linux Kernel Module to Verify Temporal Properties of a Task Schedule. In 36th Euromicro Conference on Real-Time Systems (ECRTS 2024). Leibniz International Proceedings in Informatics (LIPIcs), Volume 298, pp. 2:1-2:24, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2024)
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@InProceedings{castrovilli_et_al:LIPIcs.ECRTS.2024.2,
author = {Castrovilli, Michele and Bini, Enrico},
title = {{SlackCheck: A Linux Kernel Module to Verify Temporal Properties of a Task Schedule}},
booktitle = {36th Euromicro Conference on Real-Time Systems (ECRTS 2024)},
pages = {2:1--2:24},
series = {Leibniz International Proceedings in Informatics (LIPIcs)},
ISBN = {978-3-95977-324-9},
ISSN = {1868-8969},
year = {2024},
volume = {298},
editor = {Pellizzoni, Rodolfo},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2024.2},
URN = {urn:nbn:de:0030-drops-203054},
doi = {10.4230/LIPIcs.ECRTS.2024.2},
annote = {Keywords: Linux scheduler, Runtime verification, bounded-delay resource partition, supply function, service curve, real-time calculus, network calculus}
}
Document
Reachability-Based Response-Time Analysis of Preemptive Tasks Under Global Scheduling
Abstract
Global scheduling reduces the average response times as it can use the available computing cores more efficiently for scheduling ready tasks. However, this flexibility poses challenges in accurately quantifying interference scenarios, often resulting in either conservative response-time analyses or scalability issues. In this paper, we present a new response-time analysis for preemptive periodic tasks (or job sets) subject to release jitter under global job-level fixed-priority (JLFP) scheduling. Our analysis relies on the notion of schedule-abstraction graph (SAG), a reachability-based response-time analysis known for its potential accuracy and efficiency. Up to this point, SAG was limited to non-preemptive tasks due to the complexity of handling preemption when the number of preemptions and the moments they occur are not known beforehand. In this paper, we introduce the concept of time partitions and demonstrate how it facilitates the extension of SAG for preemptive tasks. Moreover, our paper provides the first response-time analysis for the global EDF(k) policy - a JLFP scheduling policy introduced in 2003 to address the Dhall’s effect.
Our experiments show that our analysis is significantly more accurate compared to the state-of-the-art analyses. For example, we identify 12 times more schedulable task sets than existing tests for the global EDF policy (e.g., for systems with 6 to 16 tasks, 70% utilization, and 4 cores) with an average runtime of 30 minutes. We show that EDF(k) outperforms global RM and EDF by scheduling on average 24.9% more task sets (e.g., for systems with 2 to 10 cores and 70% utilization). Moreover, for the first time, we show that global JLFP scheduling policies (particularly, global EDF(k)) are able to schedule task sets that are not schedulable using well-known partitioning heuristics.
Cite as
Pourya Gohari, Jeroen Voeten, and Mitra Nasri. Reachability-Based Response-Time Analysis of Preemptive Tasks Under Global Scheduling. In 36th Euromicro Conference on Real-Time Systems (ECRTS 2024). Leibniz International Proceedings in Informatics (LIPIcs), Volume 298, pp. 3:1-3:24, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2024)
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@InProceedings{gohari_et_al:LIPIcs.ECRTS.2024.3,
author = {Gohari, Pourya and Voeten, Jeroen and Nasri, Mitra},
title = {{Reachability-Based Response-Time Analysis of Preemptive Tasks Under Global Scheduling}},
booktitle = {36th Euromicro Conference on Real-Time Systems (ECRTS 2024)},
pages = {3:1--3:24},
series = {Leibniz International Proceedings in Informatics (LIPIcs)},
ISBN = {978-3-95977-324-9},
ISSN = {1868-8969},
year = {2024},
volume = {298},
editor = {Pellizzoni, Rodolfo},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2024.3},
URN = {urn:nbn:de:0030-drops-203064},
doi = {10.4230/LIPIcs.ECRTS.2024.3},
annote = {Keywords: Response-time analysis, global scheduling, preemptive, job-level fixed-priority scheduling policy, multicore, schedule-abstraction graph}
}
Document
Tighter Worst-Case Response Time Bounds for Jitter-Based Self-Suspension Analysis
Abstract
Tasks are called self-suspending if they can yield their ready state (specifically, releasing the processor while having highest priority) despite being incomplete, for instance, to offload computation to an external device or when waiting on access rights for shared resources or data. This self-suspending behavior requires special treatment when applying analytical results to compute worst-case response time bounds. One typical treatment is modeling self-suspension as release jitter in a so-called jitter-based analysis. The state of the art, when considering task-level fixed-priority scheduling, individually quantifies the jitter term of each higher-priority task by its worst-case response time minus its worst-case execution time.
This work tightens the jitter term by taking the execution behavior of the other higher-priority tasks into account. Our improved jitter-based analysis analytically dominates the previous jitter-based analysis. Moreover, an evaluation for synthetically generated sporadic tasks demonstrates that this jitter term results in tighter worst-case response time bounds for self-suspending tasks. We observe an improvement for up to 55.89 % of the tasksets compared to the previous jitter-based analysis.
Cite as
Mario Günzel, Georg von der Brüggen, and Jian-Jia Chen. Tighter Worst-Case Response Time Bounds for Jitter-Based Self-Suspension Analysis. In 36th Euromicro Conference on Real-Time Systems (ECRTS 2024). Leibniz International Proceedings in Informatics (LIPIcs), Volume 298, pp. 4:1-4:24, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2024)
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@InProceedings{gunzel_et_al:LIPIcs.ECRTS.2024.4,
author = {G\"{u}nzel, Mario and von der Br\"{u}ggen, Georg and Chen, Jian-Jia},
title = {{Tighter Worst-Case Response Time Bounds for Jitter-Based Self-Suspension Analysis}},
booktitle = {36th Euromicro Conference on Real-Time Systems (ECRTS 2024)},
pages = {4:1--4:24},
series = {Leibniz International Proceedings in Informatics (LIPIcs)},
ISBN = {978-3-95977-324-9},
ISSN = {1868-8969},
year = {2024},
volume = {298},
editor = {Pellizzoni, Rodolfo},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2024.4},
URN = {urn:nbn:de:0030-drops-203074},
doi = {10.4230/LIPIcs.ECRTS.2024.4},
annote = {Keywords: Worst-Case Response Time, WCRT, Jitter, Self-Suspension, Analysis}
}
Document
Shared Resource Contention in MCUs: A Reality Check and the Quest for Timeliness
Abstract
Microcontrollers (MCUs) are steadily embracing multi-core technology to meet growing performance demands. This trend marks a shift from their traditionally simple, deterministic designs to more complex and inherently less predictable architectures. While shared resource contention is well-studied in mid to high-end embedded systems, the emergence of multi-core architectures in MCUs introduces unique challenges and characteristics that existing research has not fully explored. In this paper, we conduct an in-depth investigation of both mainstream and next-generation MCU-based platforms, aiming to identify the sources of contention on systems typically lacking these problems. We empirically demonstrate substantial contention effects across different MCU architectures (i.e., from single- to multi-core configurations), highlighting significant application slowdowns. Notably, we observe that slowdowns can reach several orders of magnitude, with the most extreme cases showing up to a 3800x (times, not percent) increase in execution time. To address these issues, we propose and evaluate muTPArtc, a novel mechanism designed for Timely Progress Assessment (TPA) and TPA-based runtime control specifically tailored to MCUs. muTPArtc is an MCU-specialized TPA-based mechanism that leverages hardware facilities widely available in commercial off-the-shelf MCUs (i.e., hardware breakpoints and cycle counters) to successfully monitor applications' progress, detect, and mitigate timing violations. Our results demonstrate that muTPArtc effectively manages performance degradation due to interference, requiring only minimal modifications to the build pipeline and no changes to the source code of the target application, while incurring minor overheads.
Cite as
Daniel Oliveira, Weifan Chen, Sandro Pinto, and Renato Mancuso. Shared Resource Contention in MCUs: A Reality Check and the Quest for Timeliness. In 36th Euromicro Conference on Real-Time Systems (ECRTS 2024). Leibniz International Proceedings in Informatics (LIPIcs), Volume 298, pp. 5:1-5:25, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2024)
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@InProceedings{oliveira_et_al:LIPIcs.ECRTS.2024.5,
author = {Oliveira, Daniel and Chen, Weifan and Pinto, Sandro and Mancuso, Renato},
title = {{Shared Resource Contention in MCUs: A Reality Check and the Quest for Timeliness}},
booktitle = {36th Euromicro Conference on Real-Time Systems (ECRTS 2024)},
pages = {5:1--5:25},
series = {Leibniz International Proceedings in Informatics (LIPIcs)},
ISBN = {978-3-95977-324-9},
ISSN = {1868-8969},
year = {2024},
volume = {298},
editor = {Pellizzoni, Rodolfo},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2024.5},
URN = {urn:nbn:de:0030-drops-203088},
doi = {10.4230/LIPIcs.ECRTS.2024.5},
annote = {Keywords: multi-core microcontrollers, shared resources contention, progress-aware regulation}
}
Document
Optimizing Per-Core Priorities to Minimize End-To-End Latencies
Abstract
Logical Execution Time (LET) allows decoupling the schedule of real-time periodic tasks from their communication, with the advantage of isolating the communication pattern from the variability of the schedule. However, when such tasks are organized in chains, the usage of LET at the task level does not necessarily transfer the same LET properties to the chain level.
In this paper, we extend a LET-like model from tasks to chains spanning over multiple cores. We leverage the designed constant latency chains to optimize per-core priority assignment. Finally, we also provide a set of heuristic algorithms, that are compared in a large-scale experimental evaluation.
Cite as
Francesco Paladino, Alessandro Biondi, Enrico Bini, and Paolo Pazzaglia. Optimizing Per-Core Priorities to Minimize End-To-End Latencies. In 36th Euromicro Conference on Real-Time Systems (ECRTS 2024). Leibniz International Proceedings in Informatics (LIPIcs), Volume 298, pp. 6:1-6:25, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2024)
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@InProceedings{paladino_et_al:LIPIcs.ECRTS.2024.6,
author = {Paladino, Francesco and Biondi, Alessandro and Bini, Enrico and Pazzaglia, Paolo},
title = {{Optimizing Per-Core Priorities to Minimize End-To-End Latencies}},
booktitle = {36th Euromicro Conference on Real-Time Systems (ECRTS 2024)},
pages = {6:1--6:25},
series = {Leibniz International Proceedings in Informatics (LIPIcs)},
ISBN = {978-3-95977-324-9},
ISSN = {1868-8969},
year = {2024},
volume = {298},
editor = {Pellizzoni, Rodolfo},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2024.6},
URN = {urn:nbn:de:0030-drops-203094},
doi = {10.4230/LIPIcs.ECRTS.2024.6},
annote = {Keywords: Cause-Effect Chains, Logical Execution Time, End-to-End Latency, Design Optimization, Task Priorities, Data Age, Reaction Time}
}
Document
The Omnivisor: A Real-Time Static Partitioning Hypervisor Extension for Heterogeneous Core Virtualization over MPSoCs
Abstract
Following the needs of industrial applications, virtualization has emerged as one of the most effective approaches for the consolidation of mixed-criticality systems while meeting tight constraints in terms of space, weight, power, and cost (SWaP-C). In embedded platforms with homogeneous processors, a wealth of works have proposed designs and techniques to enforce spatio-temporal isolation by leveraging well-understood virtualization support. Unfortunately, achieving the same goal on heterogeneous MultiProcessor Systems-on-Chip (MPSoCs) has been largely overlooked. Modern hypervisors are designed to operate exclusively on main cores, with little or no consideration given to other co-processors within the system, such as small microcontroller-level CPUs or soft-cores deployed on programmable logic (FPGA). Typically, hypervisors consider co-processors as I/O devices allocated to virtual machines that run on primary cores, yielding full control and responsibility over them. Nevertheless, inadequate management of these resources can lead to spatio-temporal isolation issues within the system. In this paper, we propose the Omnivisor model as a paradigm for the holistic management of heterogeneous platforms. The model generalizes the features of real-time static partitioning hypervisors to enable the execution of virtual machines on processors with different Instruction Set Architectures (ISAs) within the same MPSoC. Moreover, the Omnivisor ensures temporal and spatial isolation between virtual machines by integrating and leveraging a variety of hardware and software protection mechanisms. The presented approach not only expands the scope of virtualization in MPSoCs but also enhances the overall system reliability and real-time performance for mixed-criticality applications. A full open-source reference implementation of the Omnivisor based on the Jailhouse hypervisor is provided, targeting ARM real-time processing units and RISC-V soft-cores on FPGA. Experimental results on real hardware show the benefits of the solution, including enabling the seamless launch of virtual machines on different ISAs and extending spatial/temporal isolation to heterogenous cores with enhanced regulation policies.
Cite as
Daniele Ottaviano, Francesco Ciraolo, Renato Mancuso, and Marcello Cinque. The Omnivisor: A Real-Time Static Partitioning Hypervisor Extension for Heterogeneous Core Virtualization over MPSoCs. In 36th Euromicro Conference on Real-Time Systems (ECRTS 2024). Leibniz International Proceedings in Informatics (LIPIcs), Volume 298, pp. 7:1-7:27, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2024)
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@InProceedings{ottaviano_et_al:LIPIcs.ECRTS.2024.7,
author = {Ottaviano, Daniele and Ciraolo, Francesco and Mancuso, Renato and Cinque, Marcello},
title = {{The Omnivisor: A Real-Time Static Partitioning Hypervisor Extension for Heterogeneous Core Virtualization over MPSoCs}},
booktitle = {36th Euromicro Conference on Real-Time Systems (ECRTS 2024)},
pages = {7:1--7:27},
series = {Leibniz International Proceedings in Informatics (LIPIcs)},
ISBN = {978-3-95977-324-9},
ISSN = {1868-8969},
year = {2024},
volume = {298},
editor = {Pellizzoni, Rodolfo},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2024.7},
URN = {urn:nbn:de:0030-drops-203107},
doi = {10.4230/LIPIcs.ECRTS.2024.7},
annote = {Keywords: Mixed-Criticality, Embedded Virtualization, Real-Time Systems, MPSoCs}
}
Document
Deadline Miss Early Detection Method for DAG Tasks Considering Variable Execution Time
Abstract
Autonomous driving systems must guarantee safety, which requires strict real-time performance. A series of processes, from sensor data input to vehicle control command output, must be completed by the end-to-end deadline. If a deadline miss occurs, the system must quickly transition to a safe state. To improve safety, an early detection method for deadline misses was proposed. The proposed method represents the autonomous driving system as a directed acyclic graph (DAG) with a mixture of timer-driven and event-driven nodes. It assigns appropriate time constraints for each node based on the end-to-end deadline. However, the existing methods assume the worst-case execution time (WCET) for calculating the time constraints of each node and do not consider the execution time variation of nodes, making the detection of deadline misses pessimistic. This paper proposes a deadline miss early detection method to determine the possibility of deadline misses quantitatively at the beginning of each node execution in a DAG task. It calculates the time constraints of each node using probabilistic execution time, which treats execution time as a random variable. Experimental evaluation shows that the proposed method reduces pessimism, which is a problem of conventional methods using WCET, and then achieves more accurate early detection of deadline misses. The evaluation also indicates that the execution time of static analysis required for deadline miss early detection is within a practical level.
Cite as
Hayate Toba and Takuya Azumi. Deadline Miss Early Detection Method for DAG Tasks Considering Variable Execution Time. In 36th Euromicro Conference on Real-Time Systems (ECRTS 2024). Leibniz International Proceedings in Informatics (LIPIcs), Volume 298, pp. 8:1-8:21, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2024)
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@InProceedings{toba_et_al:LIPIcs.ECRTS.2024.8,
author = {Toba, Hayate and Azumi, Takuya},
title = {{Deadline Miss Early Detection Method for DAG Tasks Considering Variable Execution Time}},
booktitle = {36th Euromicro Conference on Real-Time Systems (ECRTS 2024)},
pages = {8:1--8:21},
series = {Leibniz International Proceedings in Informatics (LIPIcs)},
ISBN = {978-3-95977-324-9},
ISSN = {1868-8969},
year = {2024},
volume = {298},
editor = {Pellizzoni, Rodolfo},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2024.8},
URN = {urn:nbn:de:0030-drops-203116},
doi = {10.4230/LIPIcs.ECRTS.2024.8},
annote = {Keywords: Autonomous driving system, deadline miss early detection, DAG, event-driven task, timer-driven task, probabilistic execution time}
}
Document
Switching Between Left and Right Continuity in Network Calculus
Abstract
The Network Calculus theory has been designed to compute upper bounds on delay and backlog in data networks. A lot of results have been developed to address different aspects. However, they are not all compatible with each other since they make different assumptions on the continuity of a core aspect of the model (the cumulative curves). However, real systems may mix several mechanisms. When modeling such a system, one has to choose one continuity hypothesis and limit the analysis to a subset of existing results. This paper addresses the continuity problem and argues formally that continuity issues are mathematical details that can be solved as long as the min-plus properties are used (minimal and maximal service, shaping). Conversely, it gives a counter-example for properties based on strict service, requiring a generalisation of the backlogged interval notion.
Cite as
Damien Guidolin--Pina and Marc Boyer. Switching Between Left and Right Continuity in Network Calculus. In 36th Euromicro Conference on Real-Time Systems (ECRTS 2024). Leibniz International Proceedings in Informatics (LIPIcs), Volume 298, pp. 9:1-9:23, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2024)
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@InProceedings{guidolinpina_et_al:LIPIcs.ECRTS.2024.9,
author = {Guidolin--Pina, Damien and Boyer, Marc},
title = {{Switching Between Left and Right Continuity in Network Calculus}},
booktitle = {36th Euromicro Conference on Real-Time Systems (ECRTS 2024)},
pages = {9:1--9:23},
series = {Leibniz International Proceedings in Informatics (LIPIcs)},
ISBN = {978-3-95977-324-9},
ISSN = {1868-8969},
year = {2024},
volume = {298},
editor = {Pellizzoni, Rodolfo},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2024.9},
URN = {urn:nbn:de:0030-drops-203129},
doi = {10.4230/LIPIcs.ECRTS.2024.9},
annote = {Keywords: Worst-case analysis, Real-time and embedded systems, Network Calculus}
}
Document
Crêpe: Clock-Reconfiguration-Aware Preemption Control in Real-Time Systems with Devices
Abstract
The domain of energy-constrained real-time systems that are operated on modern embedded system-on-chip (SoC) platforms brings numerous novel challenges for optimal resource minimization. These modern hardware platforms offer a heterogeneous variety of features to configure the tradeoff between temporal performance and energy efficiency, which goes beyond the state-of-the-art of existing dynamic-voltage-frequency-scaling (DVFS) scheduling schemes. The control center for configuring this tradeoff on platforms are complex clock subsystems that are intertwined with requirements of the SoC’s components (e.g., transceiver/memory/sensor devices). That is, several devices have precedence constraints with respect to specific clock sources and their settings. The challenge of dynamically adapting the various clock sources to select resource-optimal configurations becomes especially challenging in the presence of asynchronous preemptions, which are inherent to systems that use devices.
In this paper, we present Crêpe, an approach to clock-reconfiguration-aware preemption control: Crêpe has an understanding of the target platform’s clock subsystem, its sleep states, and penalties to reconfigure clock sources for adapting clock frequencies. Crêpe’s hardware model is combined with an awareness of the application’s device requirements for each executed task, as well as possible interrupts that cause preemptions during runtime. Using these software/hardware constraints, Crêpe employs, in its offline phase, a mathematical formalization in order to select energy-minimal configurations while meeting given deadlines. This optimizing formalization, processed by standard mathematical solver tools, accounts for potentially occurring interrupts and the respective clock reconfigurations, which are then forwarded as alternative schedules to Crêpe’s runtime system. During runtime, the dispatcher assesses these offline-determined alternative schedules and reconfigures the clock sources for energy minimization. We developed an implementation based on a widely-used SoC platform (i.e., ESP32-C3) and an automated testbed for comprehensive energy-consumption evaluations to validate Crêpe’s claim of selecting resource-optimal settings under worst-case considerations.
Cite as
Eva Dengler and Peter Wägemann. Crêpe: Clock-Reconfiguration-Aware Preemption Control in Real-Time Systems with Devices. In 36th Euromicro Conference on Real-Time Systems (ECRTS 2024). Leibniz International Proceedings in Informatics (LIPIcs), Volume 298, pp. 10:1-10:25, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2024)
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@InProceedings{dengler_et_al:LIPIcs.ECRTS.2024.10,
author = {Dengler, Eva and W\"{a}gemann, Peter},
title = {{Cr\^{e}pe: Clock-Reconfiguration-Aware Preemption Control in Real-Time Systems with Devices}},
booktitle = {36th Euromicro Conference on Real-Time Systems (ECRTS 2024)},
pages = {10:1--10:25},
series = {Leibniz International Proceedings in Informatics (LIPIcs)},
ISBN = {978-3-95977-324-9},
ISSN = {1868-8969},
year = {2024},
volume = {298},
editor = {Pellizzoni, Rodolfo},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2024.10},
URN = {urn:nbn:de:0030-drops-203135},
doi = {10.4230/LIPIcs.ECRTS.2024.10},
annote = {Keywords: energy-constrained real-time systems, time/energy tradeoff, system-on-chip, energy-aware real-time scheduling, resource minimization, preemption control, worst-case energy consumption (WCEC), worst-case execution time (WCET), static whole-system analysis}
}
Document
Open Problem Resolved: The "Two" in Existing Multiprocessor PI-Blocking Bounds Is Fundamental
Abstract
The goal of a real-time locking protocol is to reduce any priority-inversion blocking (pi-blocking) a task may incur while waiting to access a shared resource. For mutual-exclusion sharing on an m-processor platform, the best existing lower bound on per-task pi-blocking under suspension-oblivious analysis is a (trivial) lower bound of (m-1) request lengths under any job-level fixed-priority (JLFP) scheduler. Surprisingly, most asymptotically optimal locking protocols achieve a per-task pi-blocking upper bound of (2m-1) request lengths under JLFP scheduling, even though a range of very different mechanisms are used in these protocols. This paper closes the gap between these existing lower and upper bounds by establishing a lower bound of (2m-2) request lengths under global fixed-priority (G-FP) and global earliest-deadline-first (G-EDF) scheduling. This paper also shows that worst-case per-task pi-blocking can be arbitrarily close to (2m-1) request lengths for locking protocols that satisfy a certain property that is met by most (if not all) existing locking protocols. These results imply that most known asymptotically optimal locking protocols are almost truly optimal (not just asymptotic) under G-FP and G-EDF scheduling.
Cite as
Shareef Ahmed and James H. Anderson. Open Problem Resolved: The "Two" in Existing Multiprocessor PI-Blocking Bounds Is Fundamental. In 36th Euromicro Conference on Real-Time Systems (ECRTS 2024). Leibniz International Proceedings in Informatics (LIPIcs), Volume 298, pp. 11:1-11:21, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2024)
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@InProceedings{ahmed_et_al:LIPIcs.ECRTS.2024.11,
author = {Ahmed, Shareef and Anderson, James H.},
title = {{Open Problem Resolved: The "Two" in Existing Multiprocessor PI-Blocking Bounds Is Fundamental}},
booktitle = {36th Euromicro Conference on Real-Time Systems (ECRTS 2024)},
pages = {11:1--11:21},
series = {Leibniz International Proceedings in Informatics (LIPIcs)},
ISBN = {978-3-95977-324-9},
ISSN = {1868-8969},
year = {2024},
volume = {298},
editor = {Pellizzoni, Rodolfo},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2024.11},
URN = {urn:nbn:de:0030-drops-203145},
doi = {10.4230/LIPIcs.ECRTS.2024.11},
annote = {Keywords: Real-Time Systems, Real-Time Synchronization, Multiprocessors}
}
Document
Autonomy Today: Many Delay-Prone Black Boxes
Abstract
Machine-learning (ML) technology has been a key enabler in the push towards realizing ever more sophisticated autonomous-driving features. In deploying such technology, the automotive industry has relied heavily on using "black-box" software and hardware components that were originally intended for non-safety-critical contexts, without a full understanding of their real-time capabilities. A prime example of such a component is CUDA, which is fundamental to the acceleration of ML algorithms using NVIDIA GPUs. In this paper, evidence is presented demonstrating that CUDA can cause unbounded task delays. Such delays are the result of CUDA’s usage of synchronization mechanisms in the POSIX thread (pthread) library, so the latter is implicated as a delay-prone component as well. Such synchronization delays are shown to be the source of a system failure that occurred in an actual autonomous vehicle system during testing at WeRide. Motivated by these findings, a broader experimental study is presented that demonstrates several real-time deficiencies in CUDA, the glibc pthread library, Linux, and the POSIX interface of the safety-certified QNX Operating System for Safety. Partial mitigations for these deficiencies are presented and further actions are proposed for real-time researchers and developers to integrate more complete mitigations.
Cite as
Sizhe Liu, Rohan Wagle, James H. Anderson, Ming Yang, Chi Zhang, and Yunhua Li. Autonomy Today: Many Delay-Prone Black Boxes. In 36th Euromicro Conference on Real-Time Systems (ECRTS 2024). Leibniz International Proceedings in Informatics (LIPIcs), Volume 298, pp. 12:1-12:27, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2024)
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@InProceedings{liu_et_al:LIPIcs.ECRTS.2024.12,
author = {Liu, Sizhe and Wagle, Rohan and Anderson, James H. and Yang, Ming and Zhang, Chi and Li, Yunhua},
title = {{Autonomy Today: Many Delay-Prone Black Boxes}},
booktitle = {36th Euromicro Conference on Real-Time Systems (ECRTS 2024)},
pages = {12:1--12:27},
series = {Leibniz International Proceedings in Informatics (LIPIcs)},
ISBN = {978-3-95977-324-9},
ISSN = {1868-8969},
year = {2024},
volume = {298},
editor = {Pellizzoni, Rodolfo},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2024.12},
URN = {urn:nbn:de:0030-drops-203152},
doi = {10.4230/LIPIcs.ECRTS.2024.12},
annote = {Keywords: autonomous driving, CUDA programming, locking protocols, POSIX thread, operating systems, machine learning systems, real-time systems}
}
Document
DeepTrust^RT: Confidential Deep Neural Inference Meets Real-Time!
Abstract
Deep Neural Networks (DNNs) are becoming common in "learning-enabled" time-critical applications such as autonomous driving and robotics. One approach to protect DNN inference from adversarial actions and preserve model privacy/confidentiality is to execute them within trusted enclaves available in modern processors. However, running DNN inference inside limited-capacity enclaves while ensuring timing guarantees is challenging due to (a) large size of DNN workloads and (b) extra switching between "normal" and "trusted" execution modes. This paper introduces new time-aware scheduling schemes - DeepTrust^RT - to securely execute deep neural inferences for learning-enabled real-time systems. We first propose a variant of EDF (called DeepTrust^RT-LW) that slices each DNN layer and runs them sequentially in the enclave. However, due to extra context switch overheads of individual layer slices, we further introduce a novel layer fusion technique (named DeepTrust^RT-FUSION). Our proposed scheme provides hard real-time guarantees by fusing multiple layers of DNN workload from multiple tasks; thus allowing them to fit and run concurrently within the enclaves while maintaining real-time guarantees. We implemented and tested DeepTrust^RT ideas on the Raspberry Pi platform running OP-TEE+DarkNet-TZ DNN APIs and three DNN workloads (AlexNet-squeezed, Tiny Darknet, YOLOv3-tiny). Compared to the layer-wise partitioning approach (DeepTrust^RT-LW), DeepTrust^RT-FUSION can schedule up to 3x more tasksets and reduce context switches by up to 11.12x. We further demonstrate the efficacy of DeepTrust^RT using a flight controller (ArduPilot) case study and find that DeepTrust^RT-FUSION retains real-time guarantees where DeepTrust^RT-LW becomes unschedulable.
Cite as
Mohammad Fakhruddin Babar and Monowar Hasan. DeepTrust^RT: Confidential Deep Neural Inference Meets Real-Time!. In 36th Euromicro Conference on Real-Time Systems (ECRTS 2024). Leibniz International Proceedings in Informatics (LIPIcs), Volume 298, pp. 13:1-13:24, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2024)
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@InProceedings{babar_et_al:LIPIcs.ECRTS.2024.13,
author = {Babar, Mohammad Fakhruddin and Hasan, Monowar},
title = {{DeepTrust^RT: Confidential Deep Neural Inference Meets Real-Time!}},
booktitle = {36th Euromicro Conference on Real-Time Systems (ECRTS 2024)},
pages = {13:1--13:24},
series = {Leibniz International Proceedings in Informatics (LIPIcs)},
ISBN = {978-3-95977-324-9},
ISSN = {1868-8969},
year = {2024},
volume = {298},
editor = {Pellizzoni, Rodolfo},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2024.13},
URN = {urn:nbn:de:0030-drops-203161},
doi = {10.4230/LIPIcs.ECRTS.2024.13},
annote = {Keywords: DNN, TrustZone, Real-Time Systems}
}
Document
GCAPS: GPU Context-Aware Preemptive Priority-Based Scheduling for Real-Time Tasks
Abstract
Scheduling real-time tasks that utilize GPUs with analyzable guarantees poses a significant challenge due to the intricate interaction between CPU and GPU resources, as well as the complex GPU hardware and software stack. While much research has been conducted in the real-time research community, several limitations persist, including the absence or limited availability of GPU-level preemption, extended blocking times, and/or the need for extensive modifications to program code. In this paper, we propose GCAPS, a GPU Context-Aware Preemptive Scheduling approach for real-time GPU tasks. Our approach exerts control over GPU context scheduling at the device driver level and enables preemption of GPU execution based on task priorities by simply adding one-line macros to GPU segment boundaries. In addition, we provide a comprehensive response time analysis of GPU-using tasks for both our proposed approach as well as the default Nvidia GPU driver scheduling that follows a work-conserving round-robin policy. Through empirical evaluations and case studies, we demonstrate the effectiveness of the proposed approaches in improving taskset schedulability and response time. The results highlight significant improvements over prior work as well as the default scheduling approach, with up to 40% higher schedulability, while also achieving predictable worst-case behavior on Nvidia Jetson embedded platforms.
Cite as
Yidi Wang, Cong Liu, Daniel Wong, and Hyoseung Kim. GCAPS: GPU Context-Aware Preemptive Priority-Based Scheduling for Real-Time Tasks. In 36th Euromicro Conference on Real-Time Systems (ECRTS 2024). Leibniz International Proceedings in Informatics (LIPIcs), Volume 298, pp. 14:1-14:25, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2024)
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@InProceedings{wang_et_al:LIPIcs.ECRTS.2024.14,
author = {Wang, Yidi and Liu, Cong and Wong, Daniel and Kim, Hyoseung},
title = {{GCAPS: GPU Context-Aware Preemptive Priority-Based Scheduling for Real-Time Tasks}},
booktitle = {36th Euromicro Conference on Real-Time Systems (ECRTS 2024)},
pages = {14:1--14:25},
series = {Leibniz International Proceedings in Informatics (LIPIcs)},
ISBN = {978-3-95977-324-9},
ISSN = {1868-8969},
year = {2024},
volume = {298},
editor = {Pellizzoni, Rodolfo},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2024.14},
URN = {urn:nbn:de:0030-drops-203170},
doi = {10.4230/LIPIcs.ECRTS.2024.14},
annote = {Keywords: Real-time systems, GPU scheduling}
}
Document
Predictable GPU Sharing in Component-Based Real-Time Systems
Abstract
This paper presents a real-time locking protocol whose design was motivated by the goal of enabling safe GPU sharing in time-sliced component-based systems. This locking protocol enables a GPU to be shared concurrently across, and utilized within, isolated components with predictable execution times. It relies on a novel resizing technique where GPU work is dimensioned on-the-fly to run on partitions of an NVIDIA GPU. This technique can be applied to any component that internally utilizes global CPU scheduling. The proposed locking protocol enables increased GPU parallelism and reduces GPU capacity loss with analytically provable benefits.
Cite as
Syed W. Ali, Zelin Tong, Joseph Goh, and James H. Anderson. Predictable GPU Sharing in Component-Based Real-Time Systems. In 36th Euromicro Conference on Real-Time Systems (ECRTS 2024). Leibniz International Proceedings in Informatics (LIPIcs), Volume 298, pp. 15:1-15:22, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2024)
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@InProceedings{ali_et_al:LIPIcs.ECRTS.2024.15,
author = {Ali, Syed W. and Tong, Zelin and Goh, Joseph and Anderson, James H.},
title = {{Predictable GPU Sharing in Component-Based Real-Time Systems}},
booktitle = {36th Euromicro Conference on Real-Time Systems (ECRTS 2024)},
pages = {15:1--15:22},
series = {Leibniz International Proceedings in Informatics (LIPIcs)},
ISBN = {978-3-95977-324-9},
ISSN = {1868-8969},
year = {2024},
volume = {298},
editor = {Pellizzoni, Rodolfo},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2024.15},
URN = {urn:nbn:de:0030-drops-203183},
doi = {10.4230/LIPIcs.ECRTS.2024.15},
annote = {Keywords: GPU locking protocols, real-time locking protocols, priority-inversion blocking, component-based systems}
}
Document
Analysis of TSN Time-Aware Shapers Using Schedule Abstraction Graphs
Abstract
IEEE Time-Sensitive Networking (TSN) is one of the main solutions considered by the industry to support time-sensitive communication in data-intensive safety-critical and mission-critical applications such as autonomous driving and smart manufacturing. IEEE TSN standardizes several mechanisms to support real-time traffic on Ethernet networks. Time-Aware Shapers (TAS) (IEEE 802.1Qbv) is the standardized mechanisms of TSN that is usually considered to provide the most deterministic behavior for packet forwarding. TAS regulates when traffic classes may forward incoming packets to the egress of a TSN switch using gates that are opened and closed according to a time-triggered schedule.
State-of-the-art solutions to configure or analyze TAS do not allow for multiple traffic classes to have their TAS gates opened at the same time according to any arbitrary schedule. In this paper, we present the first response-time analysis for traffic shaped with TAS where no restriction is enforced on the gate schedule. The proposed analysis is exact. It is a non-trivial variant of the schedule abstraction graph analysis framework [Nasri and Brandenburg, 2017]. Experiments confirm the usefulness of the proposed analysis and show that it is promising for doing design-space exploration where non-conventional TAS gates configurations are investigated to, for instance, improve average-case performance without degrading the worst-case.
Cite as
Srinidhi Srinivasan, Geoffrey Nelissen, Reinder J. Bril, and Nirvana Meratnia. Analysis of TSN Time-Aware Shapers Using Schedule Abstraction Graphs. In 36th Euromicro Conference on Real-Time Systems (ECRTS 2024). Leibniz International Proceedings in Informatics (LIPIcs), Volume 298, pp. 16:1-16:24, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2024)
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@InProceedings{srinivasan_et_al:LIPIcs.ECRTS.2024.16,
author = {Srinivasan, Srinidhi and Nelissen, Geoffrey and Bril, Reinder J. and Meratnia, Nirvana},
title = {{Analysis of TSN Time-Aware Shapers Using Schedule Abstraction Graphs}},
booktitle = {36th Euromicro Conference on Real-Time Systems (ECRTS 2024)},
pages = {16:1--16:24},
series = {Leibniz International Proceedings in Informatics (LIPIcs)},
ISBN = {978-3-95977-324-9},
ISSN = {1868-8969},
year = {2024},
volume = {298},
editor = {Pellizzoni, Rodolfo},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2024.16},
URN = {urn:nbn:de:0030-drops-203198},
doi = {10.4230/LIPIcs.ECRTS.2024.16},
annote = {Keywords: TSN, Time-Aware Shapers, TAS, SAG, Schedule Abstraction, latency}
}
Document
Response Time Analysis for Fixed-Priority Preemptive Uniform Multiprocessor Systems
Abstract
We present a response time analysis for global fixed-priority preemptive scheduling of constrained-deadline tasks upon a uniform multiprocessor where each processor can be characterized by a different speed. A fixed-priority scheduler assigns the jobs with the highest priorities to the fastest processors. Since determining whether all tasks can meet their deadlines is generally intractable even with identical processors, we propose two sufficient schedulability tests that calculate upper bounds on the task’s worst-case response time within polynomial and pseudo-polynomial time. The proposed tests leverage the linear programming model to upper bound the interference of the higher-priority tasks. Furthermore, we identify specific conditions and platforms upon which the problem can be solved more efficiently within linear time. These formulations are used to iteratively evaluate and refine possible solutions until a safe upper bound on the task’s worst-case response time is found. Additionally, we demonstrate that, with specific minor modifications, the proposed tests are compatible with Audsley’s optimal priority assignment. Experimental evaluations performed on synthetic task sets show that the proposed approach outperforms the state-of-the-art methods.
Cite as
Binqi Sun, Tomasz Kloda, and Marco Caccamo. Response Time Analysis for Fixed-Priority Preemptive Uniform Multiprocessor Systems. In 36th Euromicro Conference on Real-Time Systems (ECRTS 2024). Leibniz International Proceedings in Informatics (LIPIcs), Volume 298, pp. 17:1-17:24, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2024)
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@InProceedings{sun_et_al:LIPIcs.ECRTS.2024.17,
author = {Sun, Binqi and Kloda, Tomasz and Caccamo, Marco},
title = {{Response Time Analysis for Fixed-Priority Preemptive Uniform Multiprocessor Systems}},
booktitle = {36th Euromicro Conference on Real-Time Systems (ECRTS 2024)},
pages = {17:1--17:24},
series = {Leibniz International Proceedings in Informatics (LIPIcs)},
ISBN = {978-3-95977-324-9},
ISSN = {1868-8969},
year = {2024},
volume = {298},
editor = {Pellizzoni, Rodolfo},
publisher = {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
address = {Dagstuhl, Germany},
URL = {https://drops.dagstuhl.de/entities/document/10.4230/LIPIcs.ECRTS.2024.17},
URN = {urn:nbn:de:0030-drops-203201},
doi = {10.4230/LIPIcs.ECRTS.2024.17},
annote = {Keywords: Real-time scheduling, Uniform multiprocessor, Response time analysis}
}